Data
Sheet
(Pre limin ar y)
The device supports Random Data Input within a page. The column address of next data, which will be
entered, may be changed to the address which follows the Random Data Input command (85h). Random
Data Input may be operated multiple times regardless of how many times it is done in a page.
The Program Confirm command (10h) initiates the re-programming process. The internal write state
controller automatically executes the algorithms and controls timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status
Register command may be issued to read the Status Register. The system controller can detect the
completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register.
Only the Read Status command and Reset command are valid when programming is in progress. When the
Page Program is complete, the Write Status Bit (I/O0) may be checked. The internal write verify detects only
errors for 1’s that are not successfully programmed to 0’s. The command register remains in Read Status
command mode until another valid command is written to the command register.
3.16
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed
by an address input of 00h.
Note:
If you want to execute Read Status command (0x70) after Read ID sequence, you should input dummy
command (0x00) before Read Status command (0x70).
For the S34ML02G1 and S34ML04G1 devices, five read cycles sequentially output the manufacturer code
(01h), and the device code and 3rd, 4th, and 5th cycle ID, respectively. For the S34ML01G1 device, four read
cycles sequentially output the manufacturer code (01h), and the device code and 80h, 4th cycle ID,
respectively. The command register remains in Read ID mode until further commands are issued to it.
shows the operation sequence, while
to
explain the byte
meaning.
Table 3.6
Read ID for Supported Configurations
Density
1 Gb
2 Gb
4 Gb
3.3V
1 Gb
2 Gb
4 Gb
x16
01h
01h
01h
C1h
CAh
CCh
00h
90h
90h
5Dh
D5h
D5h
—
44h
54h
x8
Org
V
CC
1st
01h
01h
01h
2nd
F1h
DAh
DCh
3rd
00h
90h
90h
4th
1Dh
95h
95h
5th
—
44h
54h
Table 3.7
Read ID Bytes
Device Identifier Byte
1st
2nd
3rd
4th
5th
(S34ML02G1, S34ML04G1)
Manufacturer Code
Device Identifier
Internal chip number, cell type, etc.
Page Size, Block Size, Spare Size, Organization
Multiplane information
Description
30
Spansion
®
SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
SPANSION [ SPANSION ]
