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S29GL128P90FFIR10 参数 Datasheet PDF下载

S29GL128P90FFIR10图片预览
型号: S29GL128P90FFIR10
PDF下载: 下载PDF文件 查看货源
内容描述: 3.0伏只页面模式闪存具有90纳米的MirrorBit工艺技术 [3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology]
分类和应用: 闪存存储
文件页数/大小: 77 页 / 2742 K
品牌: SPANSION [ SPANSION ]
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D a t a S h e e t ( P r e l i m i n a r y )  
Table 6.4 S29GL128P Sector & Memory Address Map  
Uniform Sector  
Size  
Sector  
Sector  
Range  
Count  
Address Range (16-bit)  
0000000h - 000FFFFh  
:
Notes  
SA00  
:
Sector Starting Address  
64 Kword/128 Kb  
128  
SA127  
07F0000 - 7FFFFF  
Sector Ending Address  
Note  
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges  
that are not explicitly listed (such as SA001-SA510) have sector starting and ending addresses that form the same pattern as all other  
sectors of that size. For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.  
7. Device Operations  
This section describes the read, program, erase, handshaking, and reset features of the Flash devices.  
Operations are initiated by writing specific commands or a sequence with specific address and data patterns  
into the command registers (see Table 12.1 through Table 12.4). The command register itself does not  
occupy any addressable memory location; rather, it is composed of latches that store the commands, along  
with the address and data information needed to execute the command. The contents of the register serve as  
input to the internal state machine and the state machine outputs dictate the function of the device. Writing  
incorrect address and data values or writing them in an improper sequence may place the device in an  
unknown state, in which case the system must pull the RESET# pin low or power cycle the device to return  
the device to the reading array data mode.  
7.1  
Device Operation Table  
The device must be setup appropriately for each operation. Table 7.1 describes the required state of each  
control pin for any particular operation.  
Table 7.1 Device Operations  
DQ8–DQ15  
Addresses  
Operation  
CE#  
OE# WE#  
RESET#  
WP#/ACC  
(Note 1)  
DQ0–DQ7 BYTE#= VIH BYTE#= VIL  
Read  
L
L
H
H
X
H
X
H
L
H
X
AIN  
AIN  
AIN  
X
DOUT  
(Note 3)  
(Note 3)  
High-Z  
High-Z  
High-Z  
DOUT  
(Note 3)  
(Note 3)  
High-Z  
High-Z  
High-Z  
DQ8–DQ14  
= High-Z,  
DQ15 = A-1  
Write (Program/Erase)  
Accelerated Program  
Standby  
L
H
(Note 2)  
L
L
H
VHH  
H
VCC 0.3 V  
X
H
X
VCC 0.3 V  
High-Z  
High-Z  
High-Z  
Output Disable  
Reset  
L
H
L
X
X
X
X
X
Legend  
L = Logic Low = V , H = Logic High = V , V = 11.5–12.5V, X = Don’t Care, A = Address In, D = Data In, D = Data Out  
IL  
IH  
HH  
IN  
IN  
OUT  
Notes  
1. Addresses are AMax:A0 in word mode; A  
:A-1 in byte mode.  
Max  
2. If WP# = V , on the outermost sector remains protected. If WP# = V , the outermost sector is unprotected. WP# has an internal pull-up; when unconnected,  
IL  
IH  
WP# is at V . All sectors are unprotected when shipped from the factory (The Secured Silicon Sector can be factory protected depending on version ordered.)  
IH  
3.  
D
or D  
as required by command sequence, data polling, or sector protect algorithm.  
OUT  
IN  
November 8, 2007 S29GL-P_00_A7  
S29GL-P MirrorBit® Flash Family  
19