Data
Sheet
(Pre limin ar y)
11.7.5
Erase And Programming Performance
Table 11.8
Erase And Programming Performance
Parameter
Typ
0.5
S29GL128P
64
128
256
512
480
432
123
246
492
984
sec
Max
3.5
256
512
1024
2048
µs
µs
Excludes system level
overhead
sec
Excludes 00h programming
prior to erasure
Unit
sec
Comments
Sector Erase Time
Chip Erase Time
S29GL256P
S29GL512P
S29GL01GP
Total Write Buffer Time
Total Accelerated Write Buffer Programming Time
S29GL128P
Chip Program Time
S29GL256P
S29GL512P
S29GL01GP
Notes
1. Typical program and erase times assume the following conditions: 25°C, 3.6 V V
CC
, 10,000 cycles, checkerboard pattern.
2. Under worst case conditions of -40°C, V
CC
= 3.0 V, 100,000 cycles.
3. Effective write buffer specification is based upon a 32-word write buffer operation.
4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum
program times listed.
5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables
11.7.6
TSOP Pin and BGA Package Capacitance
Table 11.9
Package Capacitance
Parameter Symbol
C
IN
C
OUT
C
IN2
RESET#, WP#/ACC
CE#
Notes
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
Parameter Description
Input Capacitance
Output Capacitance
Control Pin Capacitance
Separated Control Pin
Separated Control Pin
Test Setup
V
IN
= 0
V
OUT
= 0
V
IN
= 0
V
IN
= 0
V
IN
= 0
Typ
6
10
8
42
22
Max
10
12
10
45
25
Unit
pF
pF
pF
pF
pF
66
S29GL-P MirrorBit
®
Flash Family
S29GL-P_00_A7 November 8, 2007
SPANSION [ SPANSION ]
