Da ta
Shee t
(Prelimi nar y)
Table 11.5
Power-up Sequence Timings
Parameter
t
VCS
t
VIOS
t
RH
Notes
1. V
IO
< V
CC
+ 200 mV.
2. V
IO
and V
CC
ramp must be synchronized during power up.
3. If RESET# is not stable for t
VCS
or t
VIOS
:
The device does not permit any read and write operations.
A valid read operation returns FFh.
A hardware reset is required.
4. V
CC
maximum power-up current (RST=V
IL
) is 20 mA.
Description
Reset Low Time from rising edge of V
CC
(or last Reset pulse) to
rising edge of RESET#
Reset Low Time from rising edge of V
IO
(or last Reset pulse) to
rising edge of RESET#
Reset High Time before Read
Min
Min
Min
Speed
35
35
200
Unit
µs
µs
ns
Figure 11.8
Power-up Sequence Timings
V
CC
V
IO
CE#
V
CC
min
V
IO
min
t
RH
t
VIOS
RESET#
t
VCS
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit
®
Flash Family
59
SPANSION [ SPANSION ]
