Data
Sheet
(Pre limin ar y)
8.5
Advanced Sector Protection Software Examples
Table 8.2
Sector Protection Schemes: DYB, PPB and PPB Lock Bit Combinations
Unique Device PPB Lock Bit
0 = locked
1 = unlocked
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
0
0
0
0
1
1
1
1
Sector PPB
0 = protected
1 = unprotected
0
0
1
1
0
0
1
1
Sector DYB
0 = protected
1 = unprotected
x
x
1
0
x
x
0
1
Sector Protection Status
Protected through PPB
Protected through PPB
Unprotected
Protected through DYB
Protected through PPB
Protected through PPB
Protected through DYB
Unprotected
contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the
sector. In summary, if the PPB Lock Bit is locked (set to “0”), no changes to the PPBs are allowed. The PPB
Lock Bit can only be unlocked (reset to “1”) through a hardware reset or power cycle. See also
for
an overview of the Advanced Sector Protection feature.
8.6
Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control:
When WP#/ACC is at V
IL
, the either the highest or lowest sector is locked (device specific).
There are additional methods by which intended or accidental erasure of any sectors can be prevented via
hardware means. The following subsections describes these methods:
8.6.1
WP#/ACC Method
The Write Protect feature provides a hardware method of protecting one outermost sector. This function is
provided by the WP#/ACC pin and overrides the previously discussed Sector Protection/Unprotection
method.
If the system asserts V
IL
on the WP#/ACC pin, the device disables program and erase functions in the
highest or lowest sector independently of whether the sector was protected or unprotected using the method
described in
If the system asserts V
IH
on the WP#/ACC pin, the device reverts to whether the boot sectors were last set to
be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether
they were last protected or unprotected.
The WP#/ACC pin must be held stable during a command sequence execution. WP# has an internal pull-up;
when unconnected, WP# is set at V
IH
.
Note
If WP#/ACC is at V
IL
when the device is in the standby mode, the maximum input load current is increased.
See
for details.
8.6.2
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This protects data during V
CC
power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets to reading
array data. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control inputs to prevent unintentional writes when V
CC
is greater than V
LKO
.
48
S29GL-P MirrorBit
®
Flash Family
S29GL-P_00_A7 November 8, 2007
SPANSION [ SPANSION ]
