D a t a S h e e t
Advance Information on S29GL-P Hardware Reset (RESET#)
and Power-up Sequence
Table 18. Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
Speed
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode or Write mode
tReady
Min
Min
35
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode or Write mode
tReady
35
µs
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
35
200
10
0
µs
ns
µs
ns
Reset High Time Before Read
RESET# Low to Standby Mode
RY/BY# Recovery Time
Note: CE#, OE# and WE# must be at logic high during Reset Time.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
tRH
Figure 21. Reset Timings
90
S29GL-N MirrorBit™ Flash Family
S29GL-N_00_B3 October 13, 2006
SPANSION [ SPANSION ]
