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S29GL064N90TFI070 参数 Datasheet PDF下载

S29GL064N90TFI070图片预览
型号: S29GL064N90TFI070
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆, 32兆3.0伏只页面模式闪存设有110纳米的MirrorBit工艺技术 [64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology]
分类和应用: 闪存
文件页数/大小: 79 页 / 3123 K
品牌: SPANSION [ SPANSION ]
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D a t a S h e e t  
Figure 10.3 Program Suspend/Program Resume  
Program Operation  
or Write-to-Buffer  
Sequence in Progress  
Write Program Suspend  
Command Sequence  
Write address/data  
XXXh/B0h  
Command is also valid for  
Erase-suspended-program  
operations  
Wait 20 μs  
Autoselect and SecSi Sector  
read operations are also allowed  
Read data as  
required  
Data cannot be read from erase- or  
program-suspended sectors  
Done  
No  
reading?  
Yes  
Write Program Resume  
Command Sequence  
Write address/data  
XXXh/30h  
Device reverts to  
operation prior to  
Program Suspend  
10.6 Chip Erase Command Sequence  
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock  
cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase  
command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to  
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire  
memory for an all zero data pattern prior to electrical erase. The system is not required to provide any  
controls or timings during these operations. Table 10.1 on page 51 and Table 10.3 on page 53 show the  
address and data requirements for the chip erase command sequence.  
When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no  
longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2.  
Refer to Write Operation Status on page 55 for information on these status bits.  
Any commands written during the chip erase operation are ignored. However, note that a hardware reset  
immediately terminates the erase operation. If this occurs, the chip erase command sequence should be  
reinitiated once the device returns to reading array data, to ensure data integrity.  
Figure 10.4 on page 49 illustrates the algorithm for the erase operation. Refer to Table 15.3 on page 67 for  
parameters, and Figure 15.7 on page 69 for timing diagrams.  
November 16, 2007 S29GL-N_01_09  
S29GL-N MirrorBit® Flash Family  
47  
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