P r e l i m i n a r y
Test Conditions
Table 34. Test Specifications
3.3 V
Test Condition
All Speeds
1 TTL gate
Unit
Output Load
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
L
6.2 kΩ
0.0 or V
CC
Input timing measurement
reference levels (See Note)
0.5 V
0.5 V
V
V
CC
Output timing measurement
reference levels
CC
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
V
CC
0.5 V
Input
0.5 V
Measurement Level
Output
CC
CC
0.0 V
Figure 12. Input Waveforms and
Measurement Levels
April 30, 2004 S29GLxxxM_00A5
S29GLxxxM MirrorBitTM Flash Family
123
SPANSION [ SPANSION ]
