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S29AL032D70BFI030 参数 Datasheet PDF下载

S29AL032D70BFI030图片预览
型号: S29AL032D70BFI030
PDF下载: 下载PDF文件 查看货源
内容描述: 32兆位CMOS 3.0伏只快闪记忆体 [32 Megabit CMOS 3.0 Volt-only Flash Memory]
分类和应用:
文件页数/大小: 69 页 / 1731 K
品牌: SPANSION [ SPANSION ]
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A d v a n c e I n f o r m a t i o n  
without raising any device pin to a high voltage. Note that this method is only applicable to  
the Secured Silicon Sector.  
„
To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm  
shown in Figure 3, on page 27.  
Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured  
Silicon Sector Region command sequence to return to reading and writing the remainder of the  
array.  
The Secured Silicon Sector protection must be used with caution since, once protected, there is  
no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in  
the Secured Silicon Sector memory space can be modified in any way.  
START  
If data = 00h,  
RESET# =  
SecSi Sector is  
VIH or VID  
unprotected.  
If data = 01h,  
SecSi Sector is  
protected.  
Wait 1 μs  
Write 60h to  
any address  
Remove VIH or VID  
from RESET#  
Write 40h to SecSi  
Sector address  
Write reset  
with A6 = 0,  
command  
A1 = 1, A0 = 0  
SecSi Sector  
Read from SecSi  
Protect Verify  
Sector address  
complete  
with A6 = 0,  
A1 = 1, A0 = 0  
Figure 3. Secured Silicon Sector Protect Verify  
Hardware Data Protection  
The command sequence requirement of unlock cycles for programming or erasing provides data  
protection against inadvertent writes (refer to Table 17 on page 38 for command definitions). In  
addition, the following hardware data protection measures prevent accidental erasure or pro-  
gramming, which might otherwise be caused by spurious system level signals during V  
power-up and power-down transitions, or from system noise.  
CC  
Low V  
Write Inhibit  
CC  
When V is less than V  
, the device does not accept any write cycles. This protects data during  
LKO  
CC  
V
power-up and power-down. The command register and all internal program/erase circuits are  
CC  
disabled, and the device resets. Subsequent writes are ignored until V is greater than V  
. The  
CC  
LKO  
system must provide the proper signals to the control pins to prevent unintentional writes when  
is greater than V  
V
.
LKO  
CC  
Write Pulse “Glitch” Protection  
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.  
Logical Inhibit  
Write cycles are inhibited by holding any one of OE# = V , CE# = V or WE# = V . To initiate  
IL  
IH  
IH  
a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.  
June 13, 2005 S29AL032D_00_A3 S29AL032D  
27