D a t a S h e e t
AC Characteristics
t
RC
Addresses
VA
VA
VA
t
ACC
t
CE
CE#
t
CH
t
OE
OE#
WE#
t
t
OEH
DF
t
OH
High
High
DQ7
Valid Data
Complement
Compleme
Tru
DQ0–DQ6
Status
Tru
Valid Data
Status
t
BUS
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
t
RC
Addresses
CE#
VA
VA
VA
VA
t
ACC
t
CE
t
CH
t
OE
OE#
WE#
t
t
OEH
DF
t
OH
High
DQ6/DQ2
RY/BY#
Valid
Valid
(second read)
Valid
(stops toggling)
Valid Data
(first read)
t
BUS
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
June 16, 2005 S29AL008D_00A3
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SPANSION [ SPANSION ]
