D a t a S h e e t
General Description
The S29AL008D is an 8 Mbit, 3.0 volt-only Flash memory organized as 1,048,576
bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and
48-pin TSOP packages. For more information, refer to publication number 21536.
The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data ap-
pears on DQ7–DQ0. This device requires only a single, 3.0 volt V
supply to
CC
perform read, program, and erase operations. A standard EPROM programmer
can also be used to program and erase the device.
This device is manufactured using Spansion’s 200nm process technology, and of-
fers all the features and benefits of the Am29LV800B, which was manufactured
using 0.32 µm process technology.
The standard device offers access times of 70, 90, and 120 ns, allowing high
speed microprocessors to operate without wait states. To eliminate bus conten-
tion the device contains separate chip enable (CE#), write enable (WE#) and
output enable (OE#) controls.
The device requires only a single 3.0 volt power supply for both read and write
functions. Internally generated and regulated voltages are provided for the pro-
gram and erase operations.
The device is entirely command set compatible with the JEDEC single-power-
supply Flash standard. Commands are written to the command register using
standard microprocessor write timings. Register contents serve as input to an in-
ternal state-machine that controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This
initiates the Embedded Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies proper cell margin. The
Unlock Bypass mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates
the Embedded Erase algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed) before executing the
erase operation. During erase, the device automatically times the erase pulse
widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by
observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (tog-
gle) status bits. After a program or erase cycle is completed, the device is ready
to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low V detector that automat-
CC
ically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of the sectors of memory. This can be achieved in-system or via
programming equipment.
June 16, 2005 S29AL008D_00A3
S29AL008D
3
SPANSION [ SPANSION ]
