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S29AL008D70TAI020 参数 Datasheet PDF下载

S29AL008D70TAI020图片预览
型号: S29AL008D70TAI020
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位( 1一M× 8位/ 512的K× 16位) CMOS 3.0伏只引导扇区闪存 [8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory]
分类和应用: 闪存内存集成电路光电二极管
文件页数/大小: 55 页 / 1519 K
品牌: SPANSION [ SPANSION ]
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D a t a S h e e t  
START  
Write Program  
Command Sequence  
Data Poll  
from System  
Embedded  
Program  
algorithm  
in progress  
Verify Data?  
Yes  
No  
No  
Increment Address  
Last Address?  
Yes  
Programming  
Completed  
Note: See Table 5, on page 25 for program command sequence.  
Figure 3. Program Operation  
Chip Erase Command Sequence  
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-  
tiated by writing two unlock cycles, followed by a set-up command. Two  
additional unlock write cycles are then followed by the chip erase command,  
which in turn invokes the Embedded Erase algorithm. The device does not require  
the system to preprogram prior to erase. The Embedded Erase algorithm auto-  
matically preprograms and verifies the entire memory for an all zero data pattern  
prior to electrical erase. The system is not required to provide any controls or tim-  
ings during these operations. Table 5, on page 25 shows the address and data  
requirements for the chip erase command sequence.  
Any commands written to the chip during the Embedded Erase algorithm are ig-  
nored. Note that a hardware reset during the chip erase operation immediately  
terminates the operation. The Chip Erase command sequence should be reiniti-  
ated once the device returns to reading array data, to ensure data integrity.  
The system can determine the status of the erase operation by using DQ7, DQ6,  
DQ2, or RY/BY#. See Write Operation Status, on page 27 for information on  
these status bits. When the Embedded Erase algorithm is complete, the device  
returns to reading array data and addresses are no longer latched.  
22  
S29AL008D  
S29AL008D_00A3 June 16, 2005