A d v a n c e I n f o r m a t i o n
AC Characteristics
Table 9. Read Operations
Speed
Parameter
Options
JEDEC
Std
Description
Test Setup
Min
70
90
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
70
70
90
ns
CE# = VIL
OE# = VIL
tAVQV
tACC
Address to Output Delay
Max
90
ns
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
OE# = VIL
Max
Max
Max
Max
Min
70
30
25
25
90
35
30
30
ns
ns
ns
ns
ns
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
Read
0
Output Enable
Hold Time (Note 1)
tOEH
Toggle and
Data# Polling
Min
Min
10
ns
ns
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
tAXQX
tOH
0
Notes:
1. Not 100% tested.
2. See Figure 11, on page 35 and Table 8 on page 35 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operations Timings
February 18, 2005 S29AL004D_00_A1
S29AL004D
37
SPANSION [ SPANSION ]
