MBM29DL32XTE/BE80/90
(Continued)
In the MBM29DL32XTE/BE, a new design concept is implemented, so called “Sliding Bank Architecture”. Under
this concept, the MBM29DL32XTE/BE can be produced a series of devices with different Bank 1/Bank 2 size
combinations; 4 Mb/28 Mb, 8 Mb/24 Mb, 16 Mb/16 Mb.
To eliminate bus contention the devices have separate chip enable (CE) , write enable (WE) , and output enable
(OE) controls.
The MBM29DL32XTE/BE are pin and command set compatible with JEDEC standard E2PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations.
Typically, each sector can be programmed and verified in about 0.5 seconds.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29DL32XTE/BE are erased when shipped from the
factory.
Internallygeneratedandregulatedvoltagesareprovidedfortheprogramanderaseoperations. AlowVCC detector
automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data
Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase
cycle has been completed, the devices internally reset to the read mode.
The MBM29DL32XTE/BE memories electrically erase the entire chip or all bits within a sector simultaneously
via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM
programming mechanism of hot electron injection.
2
SPANSION [ SPANSION ]
