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AM29F010B-90JF 参数 Datasheet PDF下载

AM29F010B-90JF图片预览
型号: AM29F010B-90JF
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位( 128千×8位) CMOS 5.0伏只,统一部门快闪记忆体 [1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory]
分类和应用:
文件页数/大小: 33 页 / 1007 K
品牌: SPANSION [ SPANSION ]
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D A T A S H E E T  
mand sequence (prior to the program or erase  
operation), and during the sector erase time-out.  
During an Embedded Program or Erase algorithm op-  
eration, successive read cycles to any address cause  
DQ6 to toggle. (The system may use either OE# or  
CE# to control the read cycles.) When the operation is  
complete, DQ6 stops toggling.  
START  
Read DQ7–DQ0  
After an erase command sequence is written, if all sec-  
tors selected for erasing are protected, DQ6 toggles for  
approximately 100 μs, then returns to reading array  
data. If not all selected sectors are protected, the Em-  
bedded Erase algorithm erases the unprotected  
sectors, and ignores the selected sectors that are  
protected.  
Read DQ7–DQ0  
(Note 1)  
No  
Toggle Bit  
= Toggle?  
If a program address falls within a protected sector,  
DQ6 toggles for approximately 2 µs after the program  
command sequence is written, then returns to reading  
array data.  
Yes  
The Write Operation Status table shows the outputs for  
Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit  
algorithm, and to the Toggle Bit Timings figure in the  
“AC Characteristics” section for the timing diagram.  
No  
DQ5 = 1?  
Yes  
Reading Toggle Bit DQ6  
Refer to Figure 4 for the following discussion. When-  
ever the system initially begins reading toggle bit  
status, it must read DQ7–DQ0 at least twice in a row to  
determine whether a toggle bit is toggling. Typically, a  
system would note and store the value of the toggle bit  
after the first read. After the second read, the system  
would compare the new value of the toggle bit with the  
first. If the toggle bit is not toggling, the device has com-  
pleted the program or erase operation. The system can  
read array data on DQ7–DQ0 on the following read  
cycle.  
(Notes  
1, 2)  
Read DQ7–DQ0  
Twice  
Toggle Bit  
= Toggle?  
No  
Yes  
Program/Erase  
Operation Not  
Complete, Write  
Reset Command  
Program/Erase  
Operation Complete  
However, if after the initial two read cycles, the system  
determines that the toggle bit is still toggling, the sys-  
tem also should note whether the value of DQ5 is high  
(see the section on DQ5). If it is, the system should  
then determine again whether the toggle bit is toggling,  
since the toggle bit may have stopped toggling just as  
DQ5 went high. If the toggle bit is no longer toggling,  
the device has successfully completed the program or  
erase operation. If it is still toggling, the device did not  
complete the operation successfully, and the system  
must write the reset command to return to reading  
array data.  
Notes:  
1. Read toggle bit twice to determine whether or not it is  
toggling. See text.  
2. Recheck toggle bit because it may stop toggling as DQ5  
changes to “1”. See text.  
Figure 4. Toggle Bit Algorithm  
at the beginning of the algorithm when it returns to de-  
termine the status of the operation (top of Figure 4).  
The remaining scenario is that the system initially de-  
termines that the toggle bit is toggling and DQ5 has not  
gone high. The system may continue to monitor the  
toggle bit and DQ5 through successive read cycles, de-  
termining the status as described in the previous  
paragraph. Alternatively, it may choose to perform  
other system tasks. In this case, the system must start  
DQ5: Exceeded Timing Limits  
DQ5 indicates whether the program or erase time has  
exceeded a specified internal pulse count limit. Under  
these conditions DQ5 produces a “1.This is a failure  
condition that indicates the program or erase cycle was  
not successfully completed.  
October 31, 2006 Am29F010B_00_C7  
Am29F010B  
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