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AM29DL640H70WHI 参数 Datasheet PDF下载

AM29DL640H70WHI图片预览
型号: AM29DL640H70WHI
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位(8M ×8位/ 4米x 16位) CMOS 3.0伏只,同步读/写闪存 [64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory]
分类和应用: 闪存存储内存集成电路
文件页数/大小: 54 页 / 1243 K
品牌: SPANSION [ SPANSION ]
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GENERAL DESCRIPTION  
The Am29DL640H is a 64 megabit, 3.0 volt-only flash  
memory device, organized as 4,194,304 words of 16  
bits each or 8,388,608 bytes of 8 bits each. Word  
mode data appears on DQ15–DQ0; byte mode data  
appears on DQ7–DQ0. The device is designed to be  
programmed in-system with the standard 3.0 volt VCC  
supply, and can also be programmed in standard  
EPROM programmers.  
Factory locked parts provide several options. The Se-  
cured Silicon Sector may store a secure, random 16  
byte ESN (Electronic Serial Number), customer code  
(programmed through AMD’s ExpressFlash service),  
or both. Customer Lockable parts may utilize the Se-  
cured Silicon Sector as bonus space, reading and writ-  
ing like any other flash sector, or may permanently  
lock their own code there.  
The device is available with an access time of 55, 60,  
70, or 90 ns and is offered in 48-pin TSOP and 63-ball  
Fine Pitch BGA packages. Standard control  
pins—chip enable (CE#), write enable (WE#), and out-  
put enable (OE#)—control normal read and write op-  
erations, and avoid bus contention issues.  
DMS (Data Management Software) allows systems  
to easily take advantage of the advanced architecture  
of the simultaneous read/write product line by allowing  
removal of EEPROM devices. DMS will also allow the  
system software to be simplified, as it will perform all  
functions necessary to modify data in file structures,  
as opposed to single-byte modifications. To write or  
update a particular piece of data (a phone number or  
configuration data, for example), the user only needs  
to state which piece of data is to be updated, and  
where the updated data is located in the system. This  
is an advantage compared to systems where  
user-written software must keep track of the old data  
location, status, logical to physical translation of the  
data onto the Flash memory device (or memory de-  
vices), and more. Using DMS, user-written software  
does not need to interface with the Flash memory di-  
rectly. Instead, the user's software accesses the Flash  
memory by calling one of only six functions. AMD pro-  
vides this software to simplify system design and soft-  
ware integration efforts.  
The device requires only a single 3.0 volt power sup-  
ply for both read and write functions. Internally gener-  
ated and regulated voltages are provided for the  
program and erase operations.  
Simultaneous Read/Write Operations with  
Zero Latency  
The Simultaneous Read/Write architecture provides  
simultaneous operation by dividing the memory  
space into four banks, two 8 Mb banks with small and  
large sectors, and two 24 Mb banks of large sectors.  
Sector addresses are fixed, system software can be  
used to form user-defined bank groups.  
During an Erase/Program operation, any of the three  
non-busy banks may be read from. Note that only two  
banks can operate simultaneously. The device can im-  
prove overall system performance by allowing a host  
system to program or erase in one bank, then  
immediately and simultaneously read from the other  
bank, with zero latency. This releases the system from  
waiting for the completion of program or erase  
operations.  
The device offers complete compatibility with the  
JEDEC 42.4 single-power-supply Flash command  
set standard. Commands are written to the command  
register using standard microprocessor write timings.  
Reading data out of the device is similar to reading  
from other Flash or EPROM devices.  
The host system can detect whether a program or  
erase operation is complete by using the device sta-  
tus bits: RY/BY# pin, DQ7 (Data# Polling) and  
DQ6/DQ2 (toggle bits). After a program or erase cycle  
has been completed, the device automatically returns  
to the read mode.  
The Am29DL640H can be organized as both a top and  
bottom boot sector configuration.  
Bank  
Megabits  
Sector Sizes  
Eight 8 Kbyte/4 Kword,  
Fifteen 64 Kbyte/32 Kword  
Bank 1  
8 Mb  
The sector erase architecture allows memory sec-  
tors to be erased and reprogrammed without affecting  
the data contents of other sectors. The device is fully  
erased when shipped from the factory.  
Bank 2  
Bank 3  
24 Mb  
24 Mb  
Forty-eight 64 Kbyte/32 Kword  
Forty-eight 64 Kbyte/32 Kword  
Eight 8 Kbyte/4 Kword,  
Fifteen 64 Kbyte/32 Kword  
Bank 4  
8 Mb  
Hardware data protection measures include a low  
VCC detector that automatically inhibits write opera-  
tions during power transitions. The hardware sector  
protection feature disables both program and erase  
operations in any combination of the sectors of mem-  
ory. This can be achieved in-system or via program-  
ming equipment.  
Am29DL640H Features  
The Secured Silicon Sector is an extra 256 byte sec-  
tor capable of being permanently locked by AMD or  
customers. The Secured Silicon Customer Indicator  
Bit (DQ6) is permanently set to 1 if the part has been  
customer locked, permanently set to 0 if the part has  
been factory locked, and is 0 if customer lockable. This  
way, customer lockable parts can never be used to re-  
place a factory locked part.  
The device offers two power-saving features. When  
addresses have been stable for a specified amount of  
time, the device enters the automatic sleep mode.  
The system can also place the device into the  
standby mode. Power consumption is greatly re-  
duced in both modes.  
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Am29DL640H  
June 7, 2005  
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