Am29DL640H
64 Megabit (8 M x 8-Bit/4 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
This product has been retired and is not recommended for designs. For new and current designs, S29JL064H (for TSOP packages) and S29PL064J (for FBGA packages) supersede
DISTINCTIVE CHARACTERISTICS
AM29DL320H as the factory-recommended migration path. Please refer to each respective datasheets for specifications and ordering information. Availability of this document is retained
for reference and historical purposes only.
■ Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
ARCHITECTURAL ADVANTAGES
■ Simultaneous Read/Write operations
— 10 mA active read current at 5 MHz
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— 200 nA in standby or automatic sleep mode
— Zero latency between read and write operations
■ Minimum 1 million erase cycles guaranteed per
sector
■ Flexible BankTM architecture
■ 20 year data retention at 125°C
— Read may occur in any of the three banks not being
written or erased.
— Reliable operation for the life of the system
— Four banks may be grouped by customer to achieve
desired bank divisions.
SOFTWARE FEATURES
■ Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
■ Boot Sectors
— Top and bottom boot sectors in the same device
— Any combination of sectors can be erased
■ Supports Common Flash Memory Interface (CFI)
■ Manufactured on 0.13 µm process technology
■ Secured Silicon Sector: Extra 256 Byte sector
■ Erase Suspend/Erase Resume
— Suspends erase operations to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation.
— Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
■ Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
— Customer lockable: One-time programmable only.
Once locked, data cannot be changed
■ Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
■ Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero.
HARDWARE FEATURES
■ Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
■ Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
■ Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
PACKAGE OPTIONS
■ 63-ball Fine Pitch BGA
■ 48-pin TSOP
■ WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1,
140, and 141, regardless of sector protect status
PERFORMANCE CHARACTERISTICS
— Acceleration (ACC) function accelerates program
timing
■ High performance
— Access time as fast as 55 ns
— Program time: 4 µs/word typical using accelerated
programming function
■ Sector protection
— Hardware method to prevent any program or erase
operation within a sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
Publication# 27082 Rev: A Amendment/+7
Issue Date: June 7, 2005
Refer to AMD’s Website (www.amd.com) for the latest information.
SPANSION [ SPANSION ]
