D A T A S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std Description
Test Setup
All Speed Options
Unit
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
t
t
Max
20
µs
READY
READY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
Max
Min
Min
500
500
50
ns
ns
ns
t
RESET# Pulse Width
RP
RESET# High Time Before Read (See
Note)
t
RH
t
RESET# Low to Standby Mode
RY/BY# Recovery Time
Min
Min
20
0
µs
ns
RPD
t
RB
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 17. RESET# Timings
July 8, 2005
Am29BL162C
35
SPANSION [ SPANSION ]
