D A T A
S H E E T
BLOCK DIAGRAM OF
SIMULTANEOUS OPERATION CIRCUIT
V
CC
V
SS
Y-Decoder
Bank A Address
Latches and
Control Logic
DQ0–DQ15
Bank A
A0–A21
X-Decoder
OE#
Bank B Address
Latches and
Control Logic
Y-Decoder
DQ0–DQ15
Bank B
RESET#
WE#
CE#
AVD#
A0–A21
X-Decoder
OE#
Status
DQ0–
DQ15
PS
RDY
STATE
CONTROL
&
COMMAND
REGISTER
A0–A21
Control
OE#
DQ0–DQ15
X-Decoder
Latches and
Control Logic
Y-Decoder
Bank C Address
Bank C
DQ0–DQ15
A0–A21
A0–A21
X-Decoder
OE#
Bank D Address
Latches and
Control Logic
Y-Decoder
Bank D
DQ0–DQ15
Note:
A0–A15 are multiplexed with DQ0–DQ15.
May 8, 2006 25692A2
Am29BDS643G
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