P r e l i m i n a r y I n f o r m a t i o n
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory
location. The register is composed of latches that
store the commands, along with the address and data
information needed to execute the command. The
contents of the register serve as inputs to the internal
state machine. The state machine outputs dictate the
function of the device. Table 1 lists the device bus op-
erations, the inputs and control levels they require,
and the resulting output. The following subsections
describe each of these operations in further detail.
Table 1. Device Bus Operations
CLK
(See
Operation
CE#
OE#
L
WE# Amax–0 DQ15–0 RESET# Note) AVD#
Asynchronous Read - Addresses Latched
Asynchronous Read - Addresses Steady State
Asynchronous Write
L
L
H
H
L
Addr In
Addr In
Addr In
Addr In
HIGH Z
HIGH Z
I/O
I/O
H
H
H
H
H
L
X
X
X
L
L
L
L
H
I/O
Synchronous Write
L
H
L
I/O
Standby (CE#)
H
X
X
X
X
HIGH Z
HIGH Z
X
X
X
X
Hardware Reset
X
Burst Read Operations
Load Starting Burst Address
L
L
X
L
H
H
H
H
Addr In
HIGH Z
HIGH Z
HIGH Z
X
H
H
H
L
Advance Burst to next address with
appropriate Data presented on the Data Bus
Burst
Data Out
H
X
X
Terminate current Burst read cycle
H
X
X
X
HIGH Z
HIGH Z
Terminate current Burst read cycle via
RESET#
X
Terminate current Burst read cycle and start
new Burst read cycle
L
X
H
HIGH Z
I/O
H
Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions.
Note: Default active edge of CLK is the rising edge.
The output enable access time (t ) is the delay from
the falling edge of OE# to valid data at the output.
Requirements for Asynchronous Read
Operation (Non-Burst)
OE
The internal state machine is set for reading array
data in asynchronous mode upon device power-up, or
after a hardware reset. This ensures that no spurious
alteration of the memory content occurs during the
power transition.
To read data from the memory array, the system must
first assert a valid address on Amax–A0, while driving
AVD# and CE# to V . WE# should remain at V . The
IL
IH
rising edge of AVD# latches the address. The data will
appear on DQ15–DQ0. Since the memory array is di-
vided into four banks, each bank remains enabled for
read access until the command register contents are
altered.
Requirements for Synchronous (Burst)
Read Operation
The device is capable of continuous sequential burst
operation and linear burst operation of a preset
length. When the device first powers up, it is enabled
for asynchronous read operation.
Address access time (t
stable addresses to valid output data. The chip enable
) is equal to the delay from
ACC
access time (t ) is the delay from the stable ad-
CE
dresses and stable CE# to valid data at the outputs.
10
Am29BDS128H/Am29BDS064H
27024_A5_00_E June 18, 2004
SPANSION [ SPANSION ]
