A D V A N C E I N F O R M A T I O N
program command sequence. The unlock bypass
command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. That
bank then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. The host system may also initiate the chip
erase and sector erase sequences in the unlock
bypass mode. The erase command sequences are
four cycles in length instead of six cycles. Table 13,
“Command Definitions,” on page 28 shows the require-
ments for the unlock bypass command sequences.
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
During the unlock bypass mode, only the Unlock
Bypass Program, Unlock Bypass Sector Erase, Unlock
Bypass Chip Erase, and Unlock Bypass Reset com-
mands are valid. To exit the unlock bypass mode, the
system must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
bank address and the data 90h. The second cycle
need only contain the data 00h. The bank then returns
to the read mode.
Yes
Erasure Completed
Notes:
1. See Table 13 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
The device offers accelerated program operations
through the ACC input. When the system asserts VID
on this input, the device automatically enters the
Unlock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
ACC input to accelerate the operation.
Figure 2. Erase Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 13,
“Command Definitions,” on page 28 shows the address
and data requirements for the chip erase command
sequence.
Figure 2 illustrates the algorithm for the program oper-
ation. Refer to the Erase/Program Operations table in
the AC Characteristics section for parameters, and
Figure 21, “Asynchronous Program Operation Tim-
ings,” on page 48 for timing diagrams.
May 9, 2002
Am29BDS640G
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