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AM29BDS640GT93WSF 参数 Datasheet PDF下载

AM29BDS640GT93WSF图片预览
型号: AM29BDS640GT93WSF
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash, 4MX16, 20ns, PBGA80, 11 X 12 MM, FBGA-80]
分类和应用: 内存集成电路
文件页数/大小: 62 页 / 863 K
品牌: SPANSION [ SPANSION ]
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A D V A N C E I N F O R M A T I O N  
The reset command may be written between the  
Description  
Manufacturer ID  
Device ID, Word 1  
Address  
(BA) + 00h  
(BA) + 01h  
Read Data  
0001h  
sequence cycles in a program command sequence  
before programming begins (prior to the third cycle).  
This resets the bank to which the system was writing to  
the read mode. If the program command sequence is  
written to a bank that is in the Erase Suspend mode,  
writing the reset command returns that bank to the  
erase-suspend-read mode. Once programming  
begins, however, the device ignores reset commands  
until the operation is complete.  
227Eh  
Device ID, Word 2,  
Top Boot  
2204h (1.8 V VIO),  
2214h (3.0 V VIO)  
(BA) + 0Eh  
Device ID, Word 2,  
Bottom Boot  
2224h (1.8 V VIO),  
2234h (3.0 V VIO)  
(BA) + 0Eh  
(BA) + 0Fh  
(SA) + 02h  
Device ID, Word 3  
2201h  
The reset command may be written between the  
sequence cycles in an autoselect command sequence.  
Once in the autoselect mode, the reset command must  
be written to return to the read mode. If a bank entered  
the autoselect mode while in the Erase Suspend mode,  
writing the reset command returns that bank to the  
erase-suspend-read mode.  
Sector Block  
Lock/Unlock  
0001 (locked),  
0000 (unlocked)  
43h (provided),  
42h (not provided)  
Handshaking  
(BA) + 03h  
The system must write the reset command to return to  
the read mode (or erase-suspend-read mode if the  
bank was previously in Erase Suspend).  
If DQ5 goes high during a program or erase operation,  
writing the reset command returns the banks to the  
read mode (or erase-suspend-read mode if that bank  
was in Erase Suspend).  
Program Command Sequence  
Programming is a four-bus-cycle operation. The  
program command sequence is initiated by writing two  
unlock write cycles, followed by the program set-up  
command. The program address and data are written  
next, which in turn initiate the Embedded Program  
algorithm. The system is not required to provide further  
controls or timings. The device automatically provides  
internally generated program pulses and verifies the  
programmed cell margin. Table 13 shows the address  
and data requirements for the program command  
sequence.  
The reset command is used to exit the sector  
lock/unlock sequence.  
Autoselect Command Sequence  
The autoselect command sequence allows the host  
system to access the manufacturer and device codes,  
and determine whether or not a sector is protected.  
Table 13, “Command Definitions,” on page 28 shows  
the address and data requirements. The autoselect  
command sequence may be written to an address  
within a bank that is either in the read or erase-sus-  
pend-read mode. The autoselect command may not be  
written while the device is actively programming or  
erasing in the other bank.  
When the Embedded Program algorithm is complete,  
that bank then returns to the read mode and addresses  
are no longer latched. The system can determine the  
status of the program operation by monitoring DQ7 or  
DQ6/DQ2. Refer to the “Write Operation Status”  
section on page 29 section for information on these  
status bits.  
The autoselect command sequence is initiated by first  
writing two unlock cycles. This is followed by a third  
write cycle that contains the bank address and the  
autoselect command. The bank then enters the  
autoselect mode. No subsequent data will be made  
available if the autoselect data is read in synchronous  
mode. The system may read at any address within the  
same bank any number of times without initiating  
another autoselect command sequence. The following  
table describes the address requirements for the  
various autoselect functions, and the resulting data. BA  
represents the bank address, and SA represents the  
sector address. The device ID is read in three cycles.  
Any commands written to the device during the  
Embedded Program Algorithm are ignored. Note that a  
hardware reset immediately terminates the program  
operation. The program command sequence should be  
reinitiated once that bank has returned to the read  
mode, to ensure data integrity.  
Programming is allowed in any sequence and across  
sector boundaries. A bit cannot be programmed from  
“0” back to a “1.” Attempting to do so may cause that  
bank to set DQ5 = 1, or cause the DQ7 and DQ6 status  
bit to indicate the operation was successful. However,  
a succeeding read will show that the data is still “0.”  
Only erase operations can convert a “0” to a “1.”  
Unlock Bypass Command Sequence  
The unlock bypass feature allows the system to prima-  
rily program to a bank faster than using the standard  
24  
Am29BDS640G  
May 9, 2002  
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