A D V A N C E I N F O R M A T I O N
enabling the system to read the boot-up firmware from
Standby Mode
the Flash memory.
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
If RESET# is asserted during a program or erase oper-
ation, the device requires a time of tREADY (during
Embedded Algorithms) before the device is ready to
read data again. If RESET# is asserted when a
program or erase operation is not executing, the reset
operation is completed within a time of tREADY (not
during Embedded Algorithms). The system can read
data tRH after RESET# returns to VIH.
The device enters the CMOS standby mode when the
CE# and RESET# inputs are both held at VCC ± 0.2 V.
The device requires standard access time (tCE) for
read access, before it is ready to read data.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 20, “Reset Timings,” on
page 47 for the timing diagram.
If the device is deselected during erasure or program-
ming, the device draws active current until the opera-
tion is completed.
Output Disable Mode
ICC3 in the DC Characteristics table represents the
standby current specification.
When the OE# input is at VIH, output from the device is
disabled. The outputs are placed in the high imped-
ance state.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. While in asynchronous mode, the
device automatically enables this mode when
addresses remain stable for tACC + 60 ns. The auto-
matic sleep mode is independent of the CE#, WE#, and
OE# control signals. Standard address access timings
provide new data when addresses are changed. While
in sleep mode, output data is latched and always avail-
able to the system. While in synchronous mode, the
device automatically enables this mode when either
the first active CLK edge occurs after tACC or the CLK
runs slower than 5MHz. Note that a new burst opera-
tion is required to provide new data.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 14, “Com-
mand Definitions,” on page 29 for command defini-
tions).
The device offers two types of data protection at the
sector level:
■ The sector lock/unlock command sequence dis-
ables or re-enables both program and erase opera-
tions in any sector.
ICC4 in the “DC Characteristics” section on page 35
represents the automatic sleep mode current specifica-
tion.
■ When WP# is at VIL, sectors 0 and 1 (bottom boot)
or sectors 132 and 133 (top boot) are locked.
■ When ACC is at VIL, all sectors are locked.
The following hardware data protection measures
prevent accidental erasure or programming, which
might otherwise be caused by spurious system level
signals during VCC power-up and power-down transi-
tions, or from system noise.
RESET#: Hardware Reset Input
The RESET# input provides a hardware method of
resetting the device to reading array data. When
RESET# is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all outputs, resets the configuration
register, and ignores all read/write commands for the
duration of the RESET# pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated
once the device is ready to accept another command
sequence, to ensure data integrity.
Write Protect (WP#)
The Write Protect (WP#) input provides a hardware
method of protecting data without using VID.
If the system asserts VIL on the WP# pin, the device
disables program and erase functions in sectors 0 and
1 (bottom boot) or sectors 132 and 133 (top boot).
If the system asserts VIH on the WP# pin, the device
reverts to whether the two outermost 8K Byte boot
sectors were last set to be protected or unprotected.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS ± 0.2 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS ± 0.2 V, the standby current will
be greater.
Note that the WP# pin must not be left floating or
unconnected; inconsistent behavior of the device may
result.
RESET# may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
14
Am29BDS640G
October 31, 2002
SPANSION [ SPANSION ]
