P r e l i m i n a r y
AC Characteristics
Synchronous/Burst Read
Parameter
D8
D3
C8
C3
JEDEC Standard Description
(54 MHz) (54 MHz) (40 MHz) (40 MHz) Unit
Latency (Even Address in Reduced
Wait-State Handshaking Mode)
tIACC
Max
87.5
95
ns
Parameter
JEDEC Standard Description
D8, D9
D3, D4
C8, C9
C3, C4
(54 MHz) (54 MHz) (40 MHz) (40 MHz) Unit
Latency—(Standard Handshaking or
Odd Address in Handshake mode)
tIACC
tBACC
tACS
Max
Max
Min
Min
106
120
20
ns
ns
ns
ns
Burst Access Time Valid Clock to
Output Delay
13.5
Address Setup Time to CLK (Note
Note:)
5
Address Hold Time from CLK (Note
Note:)
tACH
7
3
tBDH
tOE
Data Hold Time from Next Clock Cycle
Output Enable to Output Valid
Chip Enable to High Z
Min
Max
Max
Max
Min
ns
ns
ns
ns
ns
ns
ns
13.5
20
tCEZ
tOEZ
tCES
tRDYS
tRACC
10
10
10.5
10.5
10
10
10.5
10.5
Output Enable to High Z
CE# Setup Time to CLK
5
RDY Setup Time to CLK
Min
5
4.5
14
5
4.5
20
Ready Access Time from CLK
Max
13.5
20
Address Setup Time to AVD# (Note
Note:)
tAAS
Min
Min
5
7
ns
ns
Address Hold Time to AVD# (Note
Note:)
tAAH
tCAS
tAVC
tAVD
tACC
CE# Setup Time to AVD#
AVD# Low to CLK
AVD# Pulse
Min
Min
Min
Max
0
5
ns
ns
ns
ns
12
70
Access Time
Note: Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
October 1, 2003 27243B1
Am29BDS320G
47
SPANSION [ SPANSION ]
