D a t a S h e e t
AC Characteristics
6
wait cycles for initial access shown.
25 ns typ. (40 MHz)
tCEZ
tCES
CE#
1
2
3
4
5
6
CLK
tAVDS
AVD#
tAVD
tACS
tBDH
Aa
A20-A0
tBACC
tACH
Hi-Z
DQ15-DQ0
tIACC
D0
D1
D2
D3
Da + n
tACC
tOEZ
tRACC
OE#
RDY
tOE
Hi-Z
Hi-Z
tRDYS
Note: Figure assumes 6 wait states for initial access, 40 MHz clock, and synchronous read. The Set Configuration Reg-
ister command sequence has been written with A18=0; device will output RDY one cycle before valid data.
Figure 15. Burst with RDY Set One Cycle Before Data
May 15, 2007 27243B2
Am29BDS320G
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