D a t a S h e e t
AC Characteristics
4 cycles for initial access shown.
tCEZ
tCES
CE#
1
2
3
4
5
CLK
tAVC
AVD#
tAVD
tACS
tBDH
Aa
A20-A0
tBACC
tACH
Hi-Z
DQ15-DQ0
tIACC
Da
Da + 1
Da + n
tACC
tOEZ
OE#
RDY
tRACC
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from
two cycles to seven cycles. Clock is set for active falling edge.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
4. In the Burst Mode Configuration Register, A17 = 0.
Figure 12. CLK Synchronous Burst Mode Read
(Falling Active Clock)
May 15, 2007 27243B2
Am29BDS320G
49
SPANSION [ SPANSION ]
