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AM29BDS64HE9VKI 参数 Datasheet PDF下载

AM29BDS64HE9VKI图片预览
型号: AM29BDS64HE9VKI
PDF下载: 下载PDF文件 查看货源
内容描述: 128或64兆比特( 8 M或4米×16位) CMOS 1.8伏只同步读/写,突发模式闪存 [128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory]
分类和应用: 闪存
文件页数/大小: 89 页 / 1587 K
品牌: SPANSION [ SPANSION ]
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D A T A S H E E T  
Embedded Algorithms) before the device is ready to  
Automatic Sleep Mode  
read data again. If RESET# is asserted when a  
program or erase operation is not executing, the reset  
The automatic sleep mode minimizes Flash device  
energy consumption. While in asynchronous mode, the  
device automatically enables this mode when  
operation is completed within a time of t  
(not  
READY  
during Embedded Algorithms). The system can read  
data t after RESET# returns to V .  
addresses remain stable for t  
+ 60 ns. The auto-  
ACC  
RH  
IH  
matic sleep mode is independent of the CE#, WE#, and  
OE# control signals. Standard address access timings  
provide new data when addresses are changed. While  
in sleep mode, output data is latched and always avail-  
able to the system. While in synchronous mode, the  
device automatically enables this mode when either the  
Refer to the “AC Characteristics” section on page 68 for  
RESET# parameters and to Figure 33, “Reset Tim-  
ings,on page 68 for the timing diagram.  
Output Disable Mode  
When the OE# input is at V , output from the device is  
first active CLK level is greater than t  
or the CLK  
IH  
ACC  
disabled. The outputs are placed in the high imped-  
ance state.  
runs slower than 5 MHz. Note that a new burst opera-  
tion is required to provide new data.  
I
in the “DC Characteristics” section on page 54  
Figure 1. Temporary Sector Unprotect Operation  
CC6  
represents the automatic sleep mode current specifica-  
tion.  
START  
RESET#: Hardware Reset Input  
The RESET# input provides a hardware method of  
resetting the device to reading array data. When  
RESET# = VID  
(Note 1)  
RESET# is driven low for at least a period of t , the  
RP  
device immediately terminates any operation in  
progress, tristates all outputs, resets the configuration  
register, and ignores all read/write commands for the  
duration of the RESET# pulse. The device also resets  
the internal state machine to reading array data. The  
operation that was interrupted should be reinitiated  
once the device is ready to accept another command  
sequence, to ensure data integrity.  
Perform Erase or  
Program Operations  
RESET# = VIH  
Temporary Sector  
Unprotect Completed  
(Note 2)  
Current is reduced for the duration of the RESET#  
pulse. When RESET# is held at V  
0.2 V, the device  
). If RESET# is held  
SS  
draws CMOS standby current (I  
CC4  
at V but not within V  
0.2 V, the standby current will  
IL  
SS  
be greater.  
Notes:  
RESET# may be tied to the system reset circuitry. A  
system reset would thus also reset the Flash memory,  
enabling the system to read the boot-up firmware from  
the Flash memory.  
1. All protected sectors unprotected (If WP# = VIL,  
outermost boot sectors will remain protected).  
2. All previously protected sectors are protected once  
again.  
If RESET# is asserted during a program or erase oper-  
ation, the device requires a time of t  
(during  
READY  
May 10, 2006 27024B3  
Am29BDS128H/Am29BDS640H  
21