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AM29BDS64HE9VKI 参数 Datasheet PDF下载

AM29BDS64HE9VKI图片预览
型号: AM29BDS64HE9VKI
PDF下载: 下载PDF文件 查看货源
内容描述: 128或64兆比特( 8 M或4米×16位) CMOS 1.8伏只同步读/写,突发模式闪存 [128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory]
分类和应用: 闪存
文件页数/大小: 89 页 / 1587 K
品牌: SPANSION [ SPANSION ]
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D A T A S H E E T  
Address 3Fh (or Offset from 3Fh by a Multiple of 64),”  
Simultaneous Read/Write Operations with  
Zero Latency  
on page 62, Figure 25, “Standard Handshake Burst  
Suspend Prior to Initial Access,on page 63, Figure 26,  
“Standard Handshake Burst Suspend at or after Initial  
Access,on page 63, Figure 27, “Standard Handshake  
Burst Suspend at Address 3Fh (Starting Address 3Dh  
or Earlier),on page 64, Figure 28, “Standard Hand-  
shake Burst Suspend at Address 3Eh/3Fh (Without a  
Valid Initial Access),on page 64, and Figure 29, “Stan-  
dard Handshake Burst Suspend at Address 3Eh/3Fh  
(with 1 Access CLK),on page 65.  
This device is capable of reading data from one bank of  
memory while programming or erasing in another bank  
of memory. An erase operation may also be suspended  
to read from or program to another location within the  
same bank (except the sector being erased).  
Figure 49, “Back-to-Back Read/Write Cycle Timings,”  
on page 83 shows how read and write cycles may be  
initiated for simultaneous operation with zero latency.  
Refer to the DC Characteristics table for  
read-while-program and read-while-erase current  
specifications.  
Burst plus Burst Suspend should not last longer than  
t
without re-latching an address or crossing an  
RCC  
address boundary. To resume the burst access, OE#  
must be re-asserted. The next active CLK edge will  
resume the burst sequence where it had been sus-  
pended. See Figure 30, “Read Cycle for Continuous  
Suspend,on page 65.  
Writing Commands/Command Sequences  
The device has the capability of performing an asyn-  
chronous or synchronous write operation. While the  
device is configured in Asynchronous read it is able to  
perform Asynchronous write operations only. CLK is  
ignored in the Asynchronous programming mode.  
When in the Synchronous read mode configuration, the  
device is able to perform both Asynchronous and Syn-  
chronous write operations. CLK and WE# address  
latch is supported in the Synchronous programming  
mode. During a synchronous write operation, to write a  
command or command sequence (which includes pro-  
gramming data to the device and erasing sectors of  
The RDY pin is only controlled by CE#. RDY will remain  
active and is not placed into a high-impedance state  
when OE# is de-asserted.  
Configuration Register  
The device uses a configuration register to set the  
various burst parameters: number of wait states, burst  
read mode, active clock edge, RDY configuration, and  
synchronous mode active.  
memory), the system must drive AVD# and CE# to V ,  
IL  
and OE# to V when providing an address to the  
IH  
Reduced Wait-state Handshaking Option  
device, and drive WE# and CE# to V , and OE# to V  
IL  
IH  
The device can be equipped with a reduced wait-state  
handshaking feature that allows the host system to  
simply monitor the RDY signal from the device to deter-  
mine when the initial word of burst data is ready to be  
read. The host system should use the programmable  
wait state configuration to set the number of wait states  
for optimal burst mode operation. The initial word of  
burst data is indicated by the rising edge of RDY after  
OE# goes low.  
when writing commands or data. During an asynchro-  
nous write operation, the system must drive CE# and  
WE# to V and OE# to V when providing an address,  
IL  
IH  
command, and data. Addresses are latched on the last  
falling edge of WE# or CE#, while data is latched on the  
1st rising edge of WE# or CE#. The asynchronous and  
synchronous programing operation is independent of  
the Set Device Read Mode bit in the Configuration  
Register (see Table 18, “Configuration Register,on  
page 36).  
The presence of the reduced wait-state handshaking  
feature may be verified by writing the autoselect  
command sequence to the device. See “Autoselect  
Command Sequence” for details.  
The device features an Unlock Bypass mode to facili-  
tate faster programming. Once the device enters the  
Unlock Bypass mode, only two write cycles are  
required to program a word, instead of four.  
For optimal burst mode performance on devices  
without the reduced wait-state handshaking option, the  
host system must set the appropriate number of wait  
states in the flash device depending on clock frequency  
and the presence of a boundary crossing. See “Set  
Configuration Register Command Sequence” section  
on page 33 section for more information. The device  
will automatically delay RDY and data by one additional  
clock cycle when the starting address is odd.  
An erase operation can erase one sector, multiple sec-  
tors, or the entire device. Table 12, “Am29BDS128H  
Sector Address Table,on page 27 indicates the  
address space that each sector occupies. The device  
address space is divided into four banks: Banks B and  
C contain only 32 Kword sectors, while Banks A and D  
contain both 4 Kword boot sectors in addition to 32  
Kword sectors. A “bank address” is the address bits  
required to uniquely select a bank. Similarly, a sector  
address” is the address bits required to uniquely select  
a sector.  
The autoselect function allows the host system to  
determine whether the flash device is enabled for  
reduced wait-state handshaking. See the “Autoselect  
Command Sequence” section for more information.  
May 10, 2006 27024B3  
Am29BDS128H/Am29BDS640H  
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