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AM29BDS64HE9VKI 参数 Datasheet PDF下载

AM29BDS64HE9VKI图片预览
型号: AM29BDS64HE9VKI
PDF下载: 下载PDF文件 查看货源
内容描述: 128或64兆比特( 8 M或4米×16位) CMOS 1.8伏只同步读/写,突发模式闪存 [128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory]
分类和应用: 闪存
文件页数/大小: 89 页 / 1587 K
品牌: SPANSION [ SPANSION ]
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D A T A S H E E T  
active clock edge, and how the RDY signal will transi-  
8-, 16-, and 32-Word Linear Burst with Wrap Around  
tion with valid data. The system would then write the  
configuration register command sequence. See “Set  
Configuration Register Command Sequence” section  
on page 33 and “Command Definitions” section on  
page 33 for further details.  
The remaining three modes are of the linear wrap  
around design, in which a fixed number of words are  
read from consecutive addresses. In each of these  
modes, the burst addresses read are determined by  
the group within which the starting address falls. The  
groups are sized according to the number of words  
read in a single burst sequence for a given mode (see  
Table 2.)  
Once the system has written the “Set Configuration  
Register” command sequence, the device is enabled  
for synchronous reads only.  
The initial word is output t  
the first CLK cycle. Subsequent words are output t  
after the active edge of  
IACC  
Table 2. Burst Address Groups  
BACC  
after the active edge of each successive clock cycle,  
which automatically increments the internal address  
counter. Note that the device has a fixed internal  
address boundary that occurs every 64 words, starting  
at address 00003Fh. During the time the device is out-  
putting data at this fixed internal address boundary  
(address 00003Fh, 00007Fh, 0000BFh, etc.), a two  
cycle latency occurs before data appears for the next  
address (address 000040h, 000080h, 0000C0h, etc.).  
The RDY output indicates this condition to the system  
by pulsing low. For standard handshaking devices,  
there is no two cycle latency between 3Fh and 40h (or  
offset from these values by a multiple of 64) if the  
latched address was 3Eh or 3Fh or offset from these  
values by a multiple of 64). See Figure 46, “Latency  
with Boundary Crossing,on page 80.  
Mode  
8-word  
16-word  
32-word  
Group Size Group Address Ranges  
8 words  
16 words  
32 words  
0-7h, 8-Fh, 10-17h,...  
0-Fh, 10-1Fh, 20-2Fh,...  
00-1Fh, 20-3Fh, 40-5Fh,...  
As an example: if the starting address in the 8-word  
mode is 39h, the address range to be read would be  
38-3Fh, and the burst sequence would be  
39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence  
begins with the starting address written to the device,  
but wraps back to the first address in the selected  
group. In a similar fashion, the 16-word and 32-word  
Linear Wrap modes begin their burst sequence on the  
starting address written to the device, and then wrap  
back to the first address in the selected address group.  
Note that in these three burst read modes the  
address pointer does not cross the boundary that  
occurs every 64 words; thus, no wait states are  
inserted (except during the initial access).  
For reduced wait-state handshaking devices, if the  
address latched is 3Eh or 3Fh (or offset from these  
values by a multiple of 64) two additional cycle latency  
occurs prior to the initial access and the two cycle  
latency between 3Fh and 40h (or offset from these  
values by a multiple of 64) will not occur.  
The RDY pin indicates when data is valid on the bus.  
The devices can wrap through a maximum of 128  
words of data (8 words up to 16 times, 16 words up to  
8 times, or 32 words up to 4 times) before requiring a  
new synchronous access (latching of a new address).  
The device will continue to output sequential burst  
data, wrapping around to address 000000h after it  
reaches the highest addressable memory location,  
until the system drives CE# high, RESET# low, or  
AVD# low in conjunction with a new address. See  
Table 1, “Device Bus Operations,on page 11.  
Burst Suspend/Resume  
The Burst Suspend/Resume feature allows the system  
to temporarily suspend a synchronous burst operation  
during the initial access (before data is available) or  
after the device is outputting data. When the burst  
operation is suspended, any previously latched internal  
data and the current state are retained.  
If the host system crosses the bank boundary while  
reading in burst mode, and the device is not program-  
ming or erasing, a two-cycle latency will occur as  
described above in the subsequent bank. If the host  
system crosses the bank boundary while the device is  
programming or erasing, the device will provide read  
status information. The clock will be ignored. After the  
host has completed status reads, or the device has  
completed the program or erase operation, the host  
can restart a burst operation using a new address and  
AVD# pulse.  
Burst Suspend requires CE# to be asserted, WE#  
de-asserted, and the initial address latched by AVD# or  
the CLK edge. Burst Suspend occurs when OE# is  
de-asserted. See Figure 21, “Reduced Wait-state  
Handshake Burst Suspend/Resume at an Even  
Address,on page 61, Figure 22, “Reduced Wait-state  
Handshake Burst Suspend/Resume at an Odd  
Address,on page 61, Figure 23, “Reduced Wait-state  
Handshake Burst Suspend/Resume at Address 3Eh  
(or Offset from 3Eh),on page 62, Figure 24, “Reduced  
Wait-state Handshake Burst Suspend/Resume at  
If the clock frequency is less than 6 MHz during a burst  
mode operation, additional latencies will occur. RDY  
indicates the length of the latency by pulsing low.  
12  
Am29BDS128H/Am29BDS640H  
27024B3 May 10, 2006