D A T A S H E E T
device will accept additional sector erase commands.
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
To ensure the command has been accepted, the
system software should check the status of DQ3 prior
to and following each subsequent sector erase com-
Table 23 shows the status of DQ3 relative to the other
status bits.
Table 23. Write Operation Status
DQ7
(Note 2)
DQ5
(Note 1)
DQ2
(Note 2)
RDY (Note
5)
Status
DQ6
DQ3
N/A
1
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
High
Impedance
1
No toggle
0
N/A
Toggle
Suspended Sector
Erase-Suspend-
Read (Note 4)
Erase
Suspend
Mode
Non-Erase
High
Impedance
Data
Data
Data
0
Data
N/A
Data
N/A
Suspended Sector
Erase-Suspend-Program
DQ7#
Toggle
0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
4. The system may read either asynchronously or synchronously (burst) while in erase suspend.
5. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress. This
is available in the Asynchronous mode only.
52
Am29BDS128H/Am29BDS640H
27024B3 May 10, 2006
SPANSION [ SPANSION ]
