P r e l i m i n a r y
I n f o r m a t i o n
Block Diagram
V
CC
V
SS
V
IO
RDY
Buffer
RDY
Erase Voltage
Generator
Input/Output
Buffers
DQ15–DQ0
WE#
RESET#
WP#
ACC
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
Data
Latch
CE#
OE#
Y-Decoder
V
CC
Detector
Y-Gating
Address Latch
Timer
X-Decoder
Cell Matrix
AVD#
CLK
Burst
State
Control
Burst
Address
Counter
Amax–A0
Note:
A
max
= A22 (128 Mb) or A21 (64 Mb)
8
Am29BDS128H/Am29BDS064H
27024_A5_00_E June 18, 2004