P r e l i m i n a r y I n f o r m a t i o n
eration is suspended, any previously latched internal
data and the current state are retained.
The presence of the reduced wait-state handshaking
feature may be verified by writing the autoselect com-
mand sequence to the device. See “Autoselect
Command Sequence” for details.
Burst Suspend requires CE# to be asserted, WE# de-
asserted, and the initial address latched by AVD# or
the CLK edge. Burst Suspend occurs when OE# is de-
asserted. See Figure 21, “Reduced Wait-state Hand-
shake Burst Suspend/Resume at an even address,” on
page 60, Figure 22, “Reduced Wait-state Handshake
Burst Suspend/Resume at an odd address,” on
page 60, Figure 23, “Reduced Wait-state Handshake
Burst Suspend/Resume at address 3Eh (or offset from
3Eh),” on page 61, Figure 24, “Reduced Wait-state
Handshake Burst Suspend/Resume at address 3Fh (or
offset from 3Fh by a multiple of 64),” on page 61,
Figure 25, “Standard Handshake Burst Suspend prior
to Initial Access,” on page 62, Figure 26, “Standard
Handshake Burst Suspend at or after Initial Access,”
on page 62, Figure 27, “Standard Handshake Burst
Suspend at address 3Fh (starting address 3Dh or ear-
lier),” on page 63, Figure 28, “Standard Handshake
Burst Suspend at address 3Eh/3Fh (without a valid
Initial Access),” on page 63, and Figure 29, “Standard
Handshake Burst Suspend at address 3Eh/3Fh (with 1
Access CLK),” on page 64.
For optimal burst mode performance on devices with-
out the reduced wait-state handshaking option, the
host system must set the appropriate number of wait
states in the flash device depending on clock fre-
quency and the presence of a boundary crossing. See
“Set Configuration Register Command Sequence” sec-
tion on page 34 section for more information. The
device will automatically delay RDY and data by one
additional clock cycle when the starting address is
odd.
The autoselect function allows the host system to de-
termine whether the flash device is enabled for
reduced wait-state handshaking. See the “Autoselect
Command Sequence” section for more information.
Simultaneous Read/Write Operations
with Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in another
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank (except the sector being
erased). Figure 49, “Back-to-Back Read/Write Cycle
Timings,” on page 82 shows how read and write cycles
may be initiated for simultaneous operation with zero
latency. Refer to the DC Characteristics table for read-
while-program and read-while-erase current
specifications.
Burst plus Burst Suspend should not last longer than
t
without re-latching an address or crossing an ad-
RCC
dress boundary. To resume the burst access, OE#
must be re-asserted. The next active CLK edge will re-
sume the burst sequence where it had been
suspended. See Figure 30, “Read Cycle for Continu-
ous Suspend,” on page 64.
The RDY pin is only controlled by CE#. RDY will remain
active and is not placed into a high-impedance state
when OE# is de-asserted.
Writing Commands/Command
Sequences
Configuration Register
The device has the capability of performing an asyn-
chronous or synchronous write operation. While the
device is configured in Asynchronous read it is able to
perform Asynchronous write operations only. CLK is
ignored in the Asynchronous programming mode.
When in the Synchronous read mode configuration,
the device is able to perform both Asynchronous and
Synchronous write operations. CLK and WE# address
latch is supported in the Synchronous programming
mode. During a synchronous write operation, to write
a command or command sequence (which includes
programming data to the device and erasing sectors
of memory), the system must drive AVD# and CE# to
V , and OE# to V when providing an address to the
The device uses a configuration register to set the var-
ious burst parameters: number of wait states, burst
read mode, active clock edge, RDY configuration, and
synchronous mode active.
Reduced Wait-state Handshaking Option
The device can be equipped with a reduced wait-state
handshaking feature that allows the host system to
simply monitor the RDY signal from the device to de-
termine when the initial word of burst data is ready to
be read. The host system should use the programma-
ble wait state configuration to set the number of wait
states for optimal burst mode operation. The initial
word of burst data is indicated by the rising edge of
RDY after OE# goes low.
IL
IH
device, and drive WE# and CE# to V , and OE# to V
IL
IH
when writing commands or data. During an asynchro-
nous write operation, the system must drive CE# and
12
Am29BDS128H/Am29BDS064H
27024_A5_00_E June 18, 2004
SPANSION [ SPANSION ]
