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AM29BDD160GT54DPBI 参数 Datasheet PDF下载

AM29BDD160GT54DPBI图片预览
型号: AM29BDD160GT54DPBI
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash, 512KX32, 54ns, PBGA80, 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80]
分类和应用: 内存集成电路闪存
文件页数/大小: 79 页 / 1482 K
品牌: SPANSION [ SPANSION ]
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PIN CONFIGURATION  
CLK  
= Clock Input that can be tied to the system  
or microprocessor clock and provides the  
fundamental timing and internal operating  
frequency.  
A–1  
= Least significant address bit for the 16-bit  
data bus, and selects between the high  
and low word. A –1 is not used for the  
32-bit mode (WORD# = VIH).  
ADV#  
IND#  
= Load Burst Address input. Indicates that  
the valid address is present on the address  
inputs.  
A0–A18  
= 19-bit address bus for 16 Mb device. A9  
supports 12 V autoselect inputs.  
DQ0–DQ31 = 32-bit data inputs/outputs/float  
= End of burst indicator for finite bursts only.  
IND is low when the last word in the burst  
sequence is at the data outputs.  
WORD#  
= Selects 16-bit or 32-bit mode. When  
WORD# = VIH, data is output on  
DQ31–DQ0. When WORD# = VIL, data is  
output on DQ15–DQ0.  
WAIT#  
WP#  
= Provides data valid feedback only when  
the burst length is set to continuous.  
CE#  
OE#  
= Chip Enable Input. This signal is asynchro-  
nous relative to CLK for the burst mode.  
= Write Protect input. When WP# = VOL, the  
two outermost bootblock sector in the 75%  
bank are write protected regardless of  
other sector protection configurations.  
= Output Enable Input. This signal is asyn-  
chronous relative to CLK for the burst  
mode.  
ACC  
= Acceleration input. When taken to 12 V,  
program and erase operations are acceler-  
ated. When not used for acceleration, ACC  
WE#  
=
Write enable. This signal is asynchronous  
relative to CLK for the burst mode.  
= VSS to VCC  
.
VSS  
= Device ground  
V
IO (VCCQ  
)
= Output Buffer Power Supply (1.65 V to  
2.75 V)  
NC  
= Pin not connected internally  
RY/BY#  
=
Ready/Busy output and open drain. When  
RY/BY# = VIH, the device is ready to ac-  
cept read operations and commands.  
When RY/BY# = VOL, the device is either  
executing an embedded algorithm or the  
device is executing a hardware reset oper-  
ation.  
VCC  
= Chip Power Supply (2.5 V to 2.75 V)  
= Hardware reset input  
RESET#  
LOGIC SYMBOLS  
x16 Mode  
x32 Mode  
20  
19  
A-1 to A18  
16  
A0–A18  
32  
DQ0–DQ15  
DQ0–DQ31  
CLK  
CLK  
CE#  
CE#  
OE#  
OE#  
WE#  
WE#  
IND/WAIT#  
RY/BY#  
IND/WAIT#  
RY/BY#  
RESET#  
ADV#  
ACC  
RESET#  
ADV#  
ACC  
WP#  
WP#  
V
IO (VCCQ  
)
VIO (VCCQ  
)
WORD#  
WORD#  
June 7, 2006  
Am29BDD160G  
9