ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1) Max (Note 2)
Unit
s
Comments
Sector Erase Time
1.0
23
18
15
8
5
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
230
250
210
130
50
s
Double Word Program Time
Word (x16) Program Time
Accelerated Double Word Program Time
Accelerated Chip Program Time
µs
µs
µs
s
Excludes system level
overhead (Note 5)
5
x16
10
12
100
120
Chip Program Time
(Note 3)
s
x32
Notes:
1. Typical program and erase times assume the following conditions: 25
typicals assume checkerboard pattern.
°C, 2.5 V VCC, 1M cycles. Additionally, programming
2. Under worst case conditions of 145°C, VCC = 2.5 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Tables 19 and 20 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1M cycles.
7. PPBs have a minimum program/erase cycle endurance of 100 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, ACC, and WP#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
VCC Current
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
PQFP AND FORTIFIED BGA PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
6
Max
7.5
12
Unit
pF
CIN
COUT
CIN2
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
8.5
7.5
pF
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
Min
10
Unit
Years
Years
150°C
125°C
Minimum Pattern Data Retention Time
20
72
Am29BDD160G
June 7, 2006
SPANSION [ SPANSION ]
