system can read CFI information at the addresses
given in Tables 13–16. To terminate reading CFI data,
the system must write the reset command.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 13–16. The
system must write the reset command to return the de-
vice to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/prod-
ucts/nvd/overview/cfi.html. Alternatively, contact an
AMD representative for copies of these documents.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The
Table 14. CFI Query Identification String
Addresses
(x32 Mode)
Addresses
(x16 Mode)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Table 15. CFI System Interface String
Addresses
(x32 Mode)
Addresses
(x16 Mode)
Data
Description
VCC Min. (write/erase)
DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt
1Bh
1Ch
36h
38h
0023h
VCC Max. (write/erase)
DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt
0027h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0004h
0000h
0009h
0000h
0005h
0000h
0007h
0000h
V
PP Min. voltage (00h = no VPP pin present)
PP Max. voltage (00h = no VPP pin present)
V
Typical timeout per single word/doubleword program 2N µs
Typical timeout for Min. size buffer program 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for word/doubleword program 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
June 7, 2006
Am29BDD160G
31
SPANSION [ SPANSION ]
