6. Executing the Chip Erase command is permitted
when the SecSi sector is enabled. The Chip Erase
command erases all sectors in the memory array
except for sector 0 in top-bootblock configuration
and sector 45 in bottom-bootblock configuration.
The SecSi Sector is a one-time programmable
memory area that cannot be erased.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes. In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
7. Executing the SecSi Sector Entry command during
program or erase suspend mode is allowed. The
Sector Erase/Program Resume command is dis-
abled while the SecSi sector is enabled, and the
user cannot resume programming of the memory
array until the Exit SecSi Sector command is writ-
ten.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal erase/program circuits are disabled,
and the device resets. Subsequent writes are ignored
until VCC is greater than VLKO. The system must pro-
vide the proper signals to the control pins to prevent
SecSi Sector Protection Bit
The SecSi Sector Protection Bit prevents program-
ming of the SecSi sector memory area. Once set, the
SecSi sector memory area contents are non-modifi-
able.
unintentional writes when VCC is greater than VLKO
.
Write Pulse “Glitch” Protection
Persistent Protection Bit Lock
Noise pulses of less than 5 ns (typical) on OE#, CE#,
or WE# do not initiate a write cycle.
The Persistent Protection Bit (PPB) Lock is a volatile
bit that reflects the state of the Password Mode Lock-
ing Bit after power-up reset. If the Password Mode
Locking Bit is set, which indicates the device is in
Password Protection Mode, the PPB Lock Bit is also
set after a hardware reset (RESET# asserted) or a
power-up reset. The ONLY means for clearing the
PPB Lock Bit in Password Protection Mode is to issue
the Password Unlock command. Successful execution
of the Password Unlock command clears the PPB
Lock Bit, allowing for sector PPBs modifications. As-
serting RESET#, taking the device through a power-on
reset, or issuing the PPB Lock Bit Set command sets
the PPB Lock Bit back to a “1”.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero (VIL) while OE#
is a logical one (VIH).
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power-up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
VCC and VIO Power-up And Power-down
Sequencing
If the Password Mode Locking Bit is not set, indicating
Persistent Sector Protection Mode, the PPB Lock Bit
is cleared after power-up or hardware reset. The PPB
Lock Bit is set by issuing the PPB Lock Bit Set com-
mand. Once set the only means for clearing the PPB
Lock Bit is by issuing a hardware or power-up reset.
The Password Unlock command is ignored in Persis-
tent Sector Protection Mode.
The device imposes no restrictions on VCC and VIO
power-up or power-down sequencing. Asserting RE-
SET# to VIL is required during the entire VCC and VIO
power sequence until the respective supplies reach
their operating voltages. Once, VCC and VIO attain their
respective operating voltages, de-assertion of RE-
SET# to VIH is permitted.
28
Am29BDD160G
June 7, 2006
SPANSION [ SPANSION ]
