Table 21. Memory Array Command Definitions (x16 Mode)
Bus Cycles (Notes 1–4)
Command (Notes)
First
Second
Third
Addr
Fourth
Fifth
Addr
Sixth
Addr Data
Addr Data Addr Data
Data
Addr
Data
Data
Read (5)
Reset (6)
1
1
4
6
4
6
6
1
1
1
2
3
4
3
2
2
1
2
RA
RD
F0
XXX
Manufacturer ID
Device ID (11)
AAA AA
AAA AA
AAA AA
AAA AA
AAA AA
555
555
555
555
555
55
55
55
55
55
AAA
AAA
AAA
AAA
AAA
90 (BA)X00
90 (BA)X02
01
7E
PD
AA
AA
Autoselect
(7)
(BA)X1C 08
(BA)X1E 00/01
Program
A0
80
80
PA
Chip Erase
Sector Erase
AAA
AAA
555
555
55
55
555
10
SA
30
Program/Erase Suspend (12)
Program/Erase Resume (13)
CFI Query (14, 15)
BA
BA
AA
XX
B0
30
98
A0
Accelerated Program (16)
Configuration Register Verify (15)
Configuration Register Write (17)
Unlock Bypass Entry (18)
Unlock Bypass Program (18)
Unlock Bypass Erase (18)
Unlock Bypass CFI (14, 18)
Unlock Bypass Reset (18)
PA
555
555
555
PA
PD
55
55
55
PD
10
AAA AA
AAA AA
AAA AA
(BA)555 C6
(BA)XX
XX
RD
AAA
AAA
D0
20
WD
XX
XX
XX
XX
A0
80
98
90
XX
XX
00
Legend:
BA = Address of the bank that is being switched to autoselect mode,
is in bypass mode, or is being erased. Determined by A18 and A17,
see Tables 11 and 12 for more detail.
PA = Program Address (A18:A-1). Addresses latch on the falling edge
of the WE# or CE# pulse, whichever happens later.
RA = Read Address (A18:A-1).
RD = Read Data (DQ15:DQ0) from location RA.
SA = Sector Address (A18:A11) for verifying (in autoselect mode),
erasing, or applying security commands.
WD = Write Data. See “Configuration Register” definition for specific
write data. Data latched on rising edge of WE#.
X = Don’t care
PD = Program Data (DQ15:DQ0) written to location PA. Data latches
on the rising edge of WE# or CE# pulse, whichever happens first.
Notes:
1. See Table 1 for description of bus operations.
9. This command is ignored during any embedded program, erase
or suspended operation.
2. All values are in hexadecimal.
10. Valid read operations include asynchronous and burst read mode
operations.
3. Shaded cells in table denote read cycles. All other cycles are
write operations.
11. The device ID must be read across the fourth, fifth, and sixth
cycles. 00h in the sixth cycle indicates top boot block, 01h
indicates bottom boot block.
4. During unlock cycles, (lower address bits are AAA or 555h as
shown in table) address bits higher than A11 (except where BA is
required) and data bits higher than DQ7 are don’t cares.
12. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Program/Erase Suspend
mode. The Program/Erase Suspend command is valid only
during a sector erase operation, and requires the bank address.
5. No unlock or command cycles required when bank is reading
array data.
6. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high (while
the bank is providing status information).
13. The Program/Erase Resume command is valid only during the
Erase Suspend mode, and requires the bank address.
14. Command is valid when device is ready to read array data or
when device is in autoselect mode.
7. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID or device ID information. See the Autoselect
Command section for more information.
15. Asynchronous read operations.
16. ACC must be at VID during the entire operation of this command.
8. This command cannot be executed until The Unlock Bypass
command must be executed before writing this command
sequence. The Unlock Bypass Reset command must be
executed to return to normal operation.
17. Command is ignored during any Embedded Program, Embedded
Erase, or Suspend operation.
18. The Unlock Bypass Entry command is required prior to any
Unlock Bypass operation. The Unlock Bypass Reset command is
required to return to the read mode.
June 7, 2006
Am29BDD160G
47
SPANSION [ SPANSION ]
