During an Embedded Program or Erase algorithm op-
eration, two immediately consecutive read cycles to
any address cause DQ6 to toggle. When the operation
is complete, DQ6 stops toggling. For asynchronous
mode, either OE# or CE# can be used to control the
read cycles. For synchronous mode, the rising edge of
ADV# is used or the rising edge of clock while ADV# is
Low.
START
Read DQ7–DQ0
Addr = VA
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are protected.
Yes
DQ7 = Data?
No
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Sus-
pend mode, DQ6 stops toggling. However, the system
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data# Poll-
ing).
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
Yes
DQ7 = Data?
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
No
Table 23 shows the outputs for Toggle Bit I on DQ6.
Figure 7 shows the toggle bit algorithm in flowchart
form, and the section Reading Toggle Bits DQ6/DQ2
explains the algorithm. Figure 25 in the AC Character-
istics section shows the toggle bit timing diagrams. Fig-
ure 25 shows the differences between DQ2 and DQ6 in
graphical form. See also the subsection on DQ2: Tog-
gle Bit II. Figure 27 shows the timing diagram for syn-
chronous toggle bit status.
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
DQ2: Toggle Bit II
Figure 6. Data# Polling Algorithm
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
DQ2 toggles when the system performs two immedi-
ately consecutive reads at addresses within those sec-
tors that have been selected for erasure. (For
asynchronous mode, either OE# or CE# can be used
to control the read cycles. For synchronous mode,
ADV# is used.) But DQ2 cannot distinguish whether
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June 7, 2006
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