enabled using a 16-bit DQ bus (WORD# = VIL), the
IND/WAIT# signal transitions active on the fourth ac-
cess. If the same scenario is used, but instead the
32-bit DQ bus is enabled, the IND/WAIT# signal transi-
tions active on the second access. The IND/WAIT#
signal has the same delay and setup timing as the DQ
pins. Also, the IND/WAIT# signal is controlled by the
OE# signal. If OE# is at VIH, the IND/WAIT# signal
floats and is not driven. If OE# is at VIL, the IND/WAIT#
signal is driven at VIH until it transitions to VIL indicating
the end of burst sequence. The IND/WAIT# signal tim-
ing and duration is (See “Configuration Register” for
more information). The following table lists the valid
combinations of the Configuration Register bits that
impact the IND/WAIT# timing.
June 7, 2006
Am29BDD160G
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