Table 5. Am29BDD160 Autoselect Codes (High Voltage Method)
A18
to
A5
to
DQ7
to
Description
CE# OE# WE# A11 A10 A9 A8 A7 A6 A4 A3 A2 A1 A0
DQ0
Manufacturer ID:
AMD
L
L
H
X
X
VID
X
X
L
X
X
X
L
L
0001h
Read Cycle 1
Read Cycle 2
L
L
L
L
H
H
X
X
X
X
VID
VID
X
X
L
L
L
L
X
L
L
L
L
H
L
007Eh
H
H
H
0008h
0000h (top boot
block)
Read Cycle 3
L
L
H
X
X
VID
X
L
L
L
H
H
H
H
0001h (bottom boot
block)
0000h (unprotected)
PPB Protection
Status
L
L
H
SA
X
VID
X
L
L
L
L
L
H
L
0001h (protected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Note: The autoselect codes may also be accessed in-system via command sequences. See Tables 18 and 20.
and should be used for device selection. OE# is the
output control and should be used to gate data to the
output pins if the device is selected.
Asynchronous Read Operation
(Non-Burst)
The device has two control functions which must be
satisfied in order to obtain data at the outputs. CE# is
the power control and should be used for device selec-
tion. OE# is the output control and should be used to
gate data to the output pins if the device is selected.
The device is power-up in an asynchronous read
mode. In the asynchronous mode the device has two
control functions which must be satisfied in order to
obtain data at the outputs. CE# is the power control
Address access time (tACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (tCE) is the delay from the stable ad-
dresses and stable CE# to valid data at the output
pins. The output enable access time is the delay from
the falling edge of OE# to valid data at the output pins
(assuming the addresses have been stable for at least
tACC–tOE time).
CE#
CLK
ADV#
A0
-A18
Address 0
Address 1
Address 2
Address 3
D0
D1
D2
D3
D3
DQ0
-
DQ31
OE#
WE#
VIH
Float
Float
VOH
IND/WAIT#
Note: Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.
Figure 1. Asynchronous Read Operation
16
Am29BDD160G
June 7, 2006
SPANSION [ SPANSION ]
