A D V A N C E I N F O R M A T I O N
tions and to Figure 15 for the timing diagram. ICC1 in
VersatileI/O™ (VIO) Control
the DC Characteristics table represents the active cur-
rent specification for reading array data.
The VersatileI/O (VIO) control allows the host system
to set the voltage levels that the device generates at
its data outputs and the voltages tolerated at its data
inputs to the same voltage level that is asserted on the
Simultaneous Read/Write Operations With
Zero Latency
V
IO pin.
The device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank (except the sector being
erased). Refer to the DC Characteristics table for
read-while-program and read-while-erase current
specifications.
The output voltage generated on the device is deter-
mined based on the VIO (VCCQ) level.
A VIO of 1.65–1.95 volts is targeted to provide for I/O
tolerance at the 1.8 volt level.
A VCC and VIO of 2.3–2.75 volts makes the device ap-
pear as 2.5 volt-only.
Address/Control signals are 3.6 V tolerant with the ex-
ception of CLK.
Simultaneous read/write operations are valid for both
the main Flash memory array and the SecSi OTP sec-
tor. Simultaneous operation is disabled during the CFI
and Password Program/Verify operations. PPB Pro-
gram/Erase operations and the Password Unlock op-
eration permit reading data from the large (75%) bank
while reading the operation status of these commands
from the small (25%) bank.
Word/Double Word Configuration
The WORD# pin controls whether the device data I/O
pins operate in the word or double word configuration.
If the WORD# pin is set at VIH, the device is in double
word configuration, DQ31–DQ0 are active and con-
trolled by CE# and OE#.
Table 2. Top Boot Bank Select
If the WORD# pin is set at VIL, the device is in word
configuration, and only data I/O pins DQ15–DQ0 are
active and controlled by CE# and OE#. The data I/O
pins DQ31–DQ16 are tri-stated.
Bank
Bank 1
Bank 2
A18:A17
00
01, 1X
Table 3. Bottom Boot Bank Select
Requirements for Reading Array Data
Bank
A18
0X, 10
11
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
Bank 1
Bank 2
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
For program operations, in the x32-mode the device
accepts program data in 32-bit words and in the x16
mode the device accepts program data in 16-bit
words.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
Sector Erase and Program Suspend Command sec-
tion has details on programming data to the device
using both standard and Unlock Bypass command se-
quences.
Address access time (tACC) is the delay from stable ad-
dresses to valid output data. The chip enable access
time (tCE) is the delay from stable addresses and sta-
ble CE# to valid data at the output pins. The output en-
able access time (tOE) is the delay from the falling
edge of OE# to valid data at the output pins (assuming
the addresses have been stable for at least tACC–tOE
time and CE# has been asserted for at least tCE–tOE
time).
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 11 and 12 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Command Definitions”
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
April 8, 2003
Am29BDD160G
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