欢迎访问ic37.com |
会员登录 免费注册
发布采购

AM28F256A-120PC 参数 Datasheet PDF下载

AM28F256A-120PC图片预览
型号: AM28F256A-120PC
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash, 32KX8, 120ns, PDIP32, PLASTIC, DIP-32]
分类和应用: 光电二极管内存集成电路
文件页数/大小: 35 页 / 461 K
品牌: SPANSION [ SPANSION ]
 浏览型号AM28F256A-120PC的Datasheet PDF文件第8页浏览型号AM28F256A-120PC的Datasheet PDF文件第9页浏览型号AM28F256A-120PC的Datasheet PDF文件第10页浏览型号AM28F256A-120PC的Datasheet PDF文件第11页浏览型号AM28F256A-120PC的Datasheet PDF文件第13页浏览型号AM28F256A-120PC的Datasheet PDF文件第14页浏览型号AM28F256A-120PC的Datasheet PDF文件第15页浏览型号AM28F256A-120PC的Datasheet PDF文件第16页  
FLASH MEMORY PROGRAM/ERASE  
OPERATIONS  
has been achieved for the memory array (no erase ver-  
ify command is required). The margin voltages are in-  
ternally generated in the same manner as when the  
standard erase verify command is used.  
Embedded Erase Algorithm  
The automatic chip erase does not require the device  
to be entirely pre-programmed prior to executing the  
Embedded set-up erase command and Embedded  
erase command. Upon executing the Embedded erase  
command the device automatically will program and  
verify the entire memory for an all zero data pattern.  
The system is not required to provide any controls or  
timing during these operations.  
The Embedded Erase Set-Up command is a command  
only operation that stages the device for automatic  
electrical erasure of all bytes in the array. Embedded  
Erase Setup is performed by writing 30h to the com-  
mand register.  
When the device is automatically verified to contain an  
all zero pattern, a self-timed chip erase and verify be-  
gin. The erase and verify operation are complete when  
the data on DQ7 is “1" (see Write Operation Status sec-  
tion) atwhich time the device returns to Read mode.  
The system is not required to provide any control or  
timing during these operations.  
To commence automatic chip erase, the command 30h  
must be written again to the command register. The au-  
tomatic erase begins on the rising edge of the WE and  
terminates when the data on DQ7 is “1" (see Write Op-  
eration Status section) at which time the device returns  
to Read mode.  
Figure 1 and Table 4 illustrate the Embedded Erase al-  
gorithm, a typical command string and bus operation.  
When using the Embedded Erase algorithm, the erase  
automatically terminates when adequate erase margin  
START  
Apply V  
PPH  
Write Embedded Erase Setup Command  
Write Embedded Erase Command  
Data# Poll from Device  
Erasure Completed  
18879C-6  
Figure 1. Embedded Erase Algorithm  
Table 4. Embedded Erase Algorithm  
Command  
Bus Operations  
Standby  
Comments  
(see Note)  
PPH  
Wait for V Ramp to V  
PP  
Embedded Erase Setup Command Data = 30h  
Embedded Erase Command Data = 30h  
Write  
Read  
Data# Polling to Verify Erasure  
Compare Output to FFh  
Standby  
Read  
Available for Read Operations  
Note: See AC and DC Characteristics for values of V parameters. The V power supply can be hard-wired to the device or  
PP  
PP  
switchable. When V is switched, V  
may be ground, no connect with a resistor tied to ground, or less than V + 2.0 V. Refer  
PP  
PPL  
CC  
to Functional Description.  
12  
Am28F256A