ERASE, PROGRAM, AND READ MODE
When VPP is equal to 12.0 V ± 5%, the command reg-
ister is active. All functions are available. That is, the
device can program, erase, read array or autoselect
data, or be standby mode.
Refer to AC Write Characteristics and the Erase/Pro-
gramming Waveforms for specific timing parameters.
Command Definitions
The contents of the command register default to 00h
(Read Mode) in the absence of high voltage applied to
the VPP pin. The device operates as a read only
memory. High voltage on the VPP pin enables the
command register. Device operations are selected by
writing specific data codes into the command register.
Table 3 in the device data sheet defines these register
commands.
Write Operations
High voltage must be applied to the V pin in order to
PP
activate the command register. Data written to the reg-
ister serves as input to the internal state machine. The
output of the state machine determines the operational
function of the device.
The command register does not occupy an address-
able memory location. The register is a latch that stores
the command, along with the address and data infor-
mation needed to execute the command. The register
is written by bringing WE# and CE# to VIL, while OE#
is at VIH. Addresses are latched on the falling edge of
WE#, while data is latched on the rising edge of the
WE# pulse. Standard microprocessor write timings are
used.
Read Command
Memory contents can be accessed via the read com-
mand when VPP is high. To read from the device, write
00h into the command register. Standard microproces-
sor read cycles access data from the memory. The de-
vice will remain in the read mode until the command
register contents are altered.
The command register defaults to 00h (read mode)
upon VPP power-up. The 00h (Read Mode) register de-
fault helps ensure that inadvertent alteration of the
memory contents does not occur during the VPP power
transition. Refer to the AC Read Characteristics and
Waveforms for the specific timing parameters.
The device requires the OE# pin to be VIH for write op-
erations. This condition eliminates the possibility for
bus contention during programming operations. In
order to write, OE# must be VIH, and CE# and WE#
must be VIL. If any pin is not in the correct state a write
command will not be executed.
Table 3. Am28F256A Command Definitions
First Bus Cycle
Second Bus Cycle
Operation
(Note 1)
Address
(Note 2)
Data
(Note 3)
Operation
(Note 1)
Address
(Note 2)
Data
(Note 3)
Command
Read Memory (Note 4)
Read Auto select
Write
Write
X
X
00h/FFh
Read
Read
RA
RD
80h or 90h
00h/01h
01h/2Fh
Embedded Erase Set-up/
Embedded Erase
Write
X
30h
Write
X
30h
Embedded Program Set-up/
Embedded Program
Write
Write
X
X
10h or 50h
00h/FFh
Write
Write
PA
X
PD
Reset (Note 4)
00h/FFh
Notes:
1. Bus operations are defined in Table 1.
2. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# pulse.
X = Don’t care.
3. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data latched on the rising edge of WE#.
4. Please reference Reset Command section.
Am28F256A
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SPANSION [ SPANSION ]
