DATA SHEET
Am29LV400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
This product has been retired and is not available for designs. For new and current designs, S29AL004D supersedes Am29LV400B and is the factory-recommended migration path. Please
refer to the S29AL004D data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
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Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations for compatibility with high
performance 3.3 volt microprocessors
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Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29LV400 device
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High performance
— Full voltage range: access times as fast as 70 ns
— Regulated voltage range: access times as fast as
55 ns
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Ultra low power consumption (typical values at
5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current
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Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
seven 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
seven 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
— A hardware method of locking a sector to prevent
any program or erase operations within that sector
— Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
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Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
■
Top or bottom boot block configurations
available
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
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Minimum 1,000,000 write cycle guarantee per sector
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20-year data retention at 125°C
— Reliable operation for the life of the system
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Package option
— 48-ball FBGA
— 48-pin TSOP
— 44-pin SO
— Lead (Pb) - Free Packaging Available
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Compatibility with JEDEC standards
— Pinout and software compatible with
single-power supply Flash
— Superior inadvertent write protection
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Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
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Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
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Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
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Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
Publication#
21523
Rev:
D
Amendment/4
Issue Date:
December 4, 2006
SPANSION [ SPANSION ]
