Data
She et
4. MCP Block Diagram
F-VCC
Flash-only Address
Shared Address
CLK
WP#
ACC
F1-CE#
OE#
WE#
F-RST#
AVD#
F2-CE#
R-VCC
22
V
CC
CLK
CE#
WE#
OE#
UB#
LB#
V
CCQ
16
VCC
VID
22
DQ15 to DQ0
CLK
WP#
ACC
Flash 1
CE#
Flash 2
OE#
WE#
RESET#
RDY
AVD#
16
DQ15 to DQ0
RDY
V
SS
I/O15 to I/O0
pSRAM
WAIT#
VSSQ
R-CE1#
R-UB#
R-LB#
R-CE2
R-CRE
AVD#
CRE#
Notes:
1. R-CRE is only present in CellularRAM-compatible pSRAM.
2. For 1 Flash + pSRAM, F1-CE# = CE#. For 2 Flash + pSRAM, CE# = F1-CE# and F2-CE# is the chip-enable pin for the second Flash.
3. Only needed for S71WS512N.
4. For the 128M pSRAM devices, there are 23 shared addresses.
5. Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S71WS-N.
5.1
Special Handling Instructions for FBGA Packages
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
April 4, 2008 S71WS-N_00_A7
S71WS-N
5
SPANSION [ SPANSION ]
