CXD3011R-1
Pin
No.
119
120
121
122
123
124
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
Symbol
I/O
Description
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low. Input when
LKIN = high. (See $3E.)
Disc innermost track detection signal input.
Digital GND.
LOCK
SSTP
DV
SS
5
DTS0
TES2
TES3
PWMI
DV
DD
5
VCOO
VCOI
TEST
PDO
VCKI
V16M
AV
DD
2
IGEN
AV
SS
2
ADIO
RFDC
CE
TE
I/O
I
1, 0
I
I
I
I
Test pin. Normally fixed to low.
Test pin. Normally fixed to low.
Test pin. Normally fixed to low.
Spindle motor external pin input.
Digital power supply.
O
I
I
O
I
O
1, 0
Analog EFM PLL oscillation circuit output.
Analog EFM PLL oscillation circuit input. flock = 8.6436MHz.
Test pin. Normally fixed to low.
1, Z, 0
Analog EFM PLL charge pump output.
Variable pitch clock input from the external VCO. fcenter = 16.9344MHz.
Set VCKI to low when the external clock is not input to this pin.
1, 0
Wide-band EFM PLL VCO2 oscillation output.
Analog power supply.
I
—
O
I
I
I
Connects the operational amplifier current source reference resistance.
Analog GND.
Operational amplifier output.
RF signal input.
Center servo analog input.
Tracking error signal input.
∗
In the CXD3011R, the following pins are NC.
Pins 1, 18 to 21, 36, 37, 53 to 56, 72, 73, 89 to 92, 108, 109, 125 to 128 and 144
Notes) •
The 64-bit slot is a LSB first, two's complement output. The 48-bit slot is a MSB first, two's complement
output.
•
GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
•
XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync
protection.
•
XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.
•
The GFS signal goes high when the frame sync and the insertion protection timing match. (See $348.)
•
RFCK is derived from the crystal accuracy, and has a cycle of 136µs. (during normal speed)
•
C2PO represents the data error status.
•
XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
–8–
SONY [ SONY CORPORATION ]
