CXD3011R-1
Pin Description
Pin
No.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
22
23
24
25
26
27
28
29
30
31
32
33
34
35
38
39
40
Symbol
SE
FE
VC
VPCO1
VPCO2
VCTL
FILO
FILI
PCO
CLTV
AV
SS
1
RFAC
BIAS
ASYI
ASYO
AV
DD
1
DV
DD
1
DV
SS
1
ASYE
PSSL
WDCK
LRCK
LRCKI
DA16
PCMDI
DA15
BCKI
DA14
DA13
DA12
DA11
DA10
DA09
I
I
O
O
I
O
I
O
I
O
O
O
O
O
O
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
I
I
I
O
1, 0
I
I
I
O
O
I
O
I
O
I
1, Z, 0
Analog
1, Z, 0
1, Z, 0
I/O
Sled error signal input.
Focus error signal input.
Center voltage input.
Wide-band EFM PLL VCO2 charge pump output.
Wide-band EFM PLL VCO2 charge pump output 2. Turned on and off by $E
command FCSW.
Wide-band EFM PLL VCO2 control voltage input.
Master PLL filter output (slave = digital PLL).
Master PLL filter input.
Master PLL charge pump output.
Multiplier VCO control voltage input.
Analog GND.
EFM signal input.
Asymmetry circuit constant current input.
Asymmetry comparator voltage input.
EFM full-swing output (low = V
SS
, high = V
DD
).
Analog power supply.
Digital power supply.
Digital GND.
Asymmetry circuit on/off (low = off, high = on).
Audio data output mode switching input (low: serial, high: parallel).
D/A interface for 48-bit slot. Word clock f = 2Fs.
D/A interface for 48-bit slot. LR clock f = Fs.
LR clock input to DAC (48-bit slot).
DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two's
complement, MSB first) when PSSL = 0.
Audio data input to DAC (48-bit slot).
DA15 output when PSSL = 1, 48-bit slot bit clock output when PSSL = 0.
Bit clock input to DAC (48-bit slot).
DA14 output when PSSL = 1, 64-bit slot serial data output (two' complement,
LSB first) when PSSL = 0.
DA13 output when PSSL = 1, 64-bit slot bit clock output when PSSL = 0.
DA12 output when PSSL = 1, 64-bit slot LR clock output when PSSL = 0.
DA11 output when PSSL = 1, GTOP output when PSSL = 0.
DA10 output when PSSL = 1, XUGF output when PSSL = 0.
DA09 output when PSSL = 1, XPLCK output when PSSL = 0.
–5–
Description
SONY [ SONY CORPORATION ]
