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CXD2510Q 参数 Datasheet PDF下载

CXD2510Q图片预览
型号: CXD2510Q
PDF下载: 下载PDF文件 查看货源
内容描述: CD数字信号处理器 [CD Digital Signal Processor]
分类和应用: 数字信号处理器
文件页数/大小: 48 页 / 710 K
品牌: SONY [ SONY CORPORATION ]
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CXD2510Q  
CLVP mode gain setting: GMDP: GMDS  
Gain  
MDP1  
Gain  
MDP0  
Gain  
MDS1  
Gain  
MDS0  
GMDP  
GMDS  
0
0
1
0
1
0
–6dB  
0dB  
0
0
1
0
1
0
–6dB  
0dB  
+6dB  
+6dB  
DCLV overall gain setting: GDCLV  
Gain  
GDCLV  
DCLV0  
0
1
0dB  
+6dB  
$DX commands  
Command  
D0  
D3  
D1  
TP  
D2  
TB  
Gain  
CLVS  
DCLV  
PWM MD  
CLV CTRL  
See the $CX commands  
Command bit  
Explanation (See the Timing Chart 1-6.)  
DCLV PWM MD = 1 Digital CLV PWM mode specified. Both MDS and MDP are used.  
DCLV PWM MD = 0 Digital CLV PWM mode specified. Ternary MDP values are output.  
Command bit  
TB = 0  
Explanation  
Bottom hold in CLVS and CLVH modes at a cycle of RFCK/32.  
Bottom hold in CLVS and CLVH modes at a cycle of RFCK/16.  
Peak hold in CLVS mode at a cycle of RFCK/4.  
TB = 1  
TP = 0  
TP = 1  
Peak hold in CLVS mode at a cycle of RFCK/2.  
Note) Peak hold is performed at 34kHz in CLVH mode.  
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