CXA3185/3186N
Description of PLL Block
The PLL on this IC supports the 3-wire bus control format.
The serial data is input to the DA, CL and CE pins. The data is loaded to the shift register at the clock rise,
and latched at the enable fall.
Symbol
CE
3-wire bus control
Enable input
CL
Clock input
DA
Data input
LOCK
Lock signal output
1) Mode Setting Method
The modes for each frequency step are set according to the MS pin voltage.
Main
divider
15 bit
14 bit
15 bit
15 bit
15 bit
Reference
divider
1024
512
Reference
frequency
Frequency
step
Control
Mode
MS pin voltage
word length
A-0
A-1
A-2
A-3
A-4
0 to 0.15VCC
OPEN
3.90625 kHz
7.8125 kHz
6.25 kHz
31.25 kHz Total 19 bits
62.5 kHz
50 kHz
Total 18 bits
Total 19 bits
Total 19 bits
Total 27 bits
0.45VCC to 0.55VCC
0.65VCC to 0.75VCC
0.85VCC to VCC
640
512
7.8125 kHz
7.8125 kHz
62.5 kHz
62.5 kHz
512
Frequency step is for when X’tal OSC = 4 MHz.
2) Programming
• The VCO lock frequency is obtained according to the following formula.
fosc = fref × 8 × (32 M + S)
fosc: local oscillator frequency
fref : reference frequency
8
: prescaler fixed frequency division ratio
: main divider frequency division ratio
: swallow counter frequency division ratio
M
S
The variable frequency division ranges of M and S are as follows, and are set as binary.
32 ≤ M ≤ 1023 (32 ≤ M ≤ 511 for A-1 mode)
0 ≤ S ≤ 31
• The PLL control data is comprised of the above frequency data and the band switch control data.
—11—
SONY [ SONY CORPORATION ]
