CXA2647N
• Center Error
The signals input to the A and D pins and the B and C pins are arithmetically amplified and the center error
signal is output.
ROM/RW switching and offset addition functions are incorporated.
VC
ROM
12k
RW
48k
200k
CEI 21
20 CE
124
A
D
B
C
6
9
7
8
30k
124
50k
30k
30k
ROM
RW
DVC
30k
24k
96k
ROM
RW
24k
96k
VOFST
CE = Gain {(B + C) – (A + D)} signal is arithmetically amplified.
Low frequency gain ROM: 15.5dB
RW: 27.5dB
Cut-off frequency fc (typ.)
ROM: 200kHz
RW: 200kHz
• Output DC Level Shift
The FE, TE and CE output DC voltages are level shifted to the digital VC voltage (DVC).
The reference voltage of this IC is the VC voltage, and only the output reference voltage changes.
The maximum output voltage of each output signal should be kept to the digital VCC voltage (DVCC) or less in
order to protect the DSP IC.
The VC and DVC voltages are arithmetically amplified
30k
and output as the VOFST voltage.
30k
The VOFST voltage serves as the level shift reference
DVC
VOFST
voltage, and is distributed to each block.
VC
15k
VOFST = 2VC –DVC
• SW
This controls the laser (APC) on/off, active/sleep mode, and ROM/RW mode switching.
Switching is controlled by the voltage applied to the SW pin.
Active/Sleep
SW low/high condition
12
SW
SW
ROM/RW
Low: GND to DVC – 1.2V
APC ON/OFF
High: DVC + 1.2V to Vcc
Status of Functions on SW Switching
Item
APC
Active/Sleep
Active
ROM/RW
The VC buffer is always in active mode
Control
voltage
even if it enters sleep mode.
In the function block, MODE SW is always
set to active mode.
VCC
ON
OFF
ON
RW
VC or Hi-Z
GND
Sleep
Active
—
ROM
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SONY [ SONY CORPORATION ]
